📄 jifei.rpt
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jifei
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - -- INPUT 0 0 0 1 aq0
43 - - - -- INPUT 0 0 0 1 aq1
60 - - C -- INPUT 0 0 0 1 aq2
58 - - C -- INPUT 0 0 0 1 aq3
1 - - - -- INPUT G 0 0 0 0 clk
48 - - - 15 INPUT 0 0 0 3 count0
47 - - - 14 INPUT 0 0 0 2 count1
39 - - - 11 INPUT 0 0 0 2 count2
38 - - - 10 INPUT 0 0 0 1 count3
84 - - - -- INPUT 0 0 0 1 dd0
44 - - - -- INPUT 0 0 0 1 dd1
50 - - - 17 INPUT 0 0 0 1 dd2
49 - - - 16 INPUT 0 0 0 1 dd3
36 - - - 07 INPUT 0 0 0 1 ko1
37 - - - 09 INPUT 0 0 0 2 ko2
30 - - C -- INPUT 0 0 0 4 load
2 - - - -- INPUT G 0 0 0 0 pg
28 - - C -- INPUT 0 0 0 24 reset
29 - - C -- INPUT 0 0 0 25 up_down
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\2502144\02502144\jifei.rpt
jifei
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
64 - - B -- OUTPUT 0 1 0 0 cout
66 - - B -- OUTPUT 0 1 0 0 out10
21 - - B -- OUTPUT 0 1 0 0 out11
22 - - B -- OUTPUT 0 1 0 0 out12
65 - - B -- OUTPUT 0 1 0 0 out13
5 - - - 05 OUTPUT 0 1 0 0 out20
6 - - - 04 OUTPUT 0 1 0 0 out21
7 - - - 03 OUTPUT 0 1 0 0 out22
8 - - - 03 OUTPUT 0 1 0 0 out23
9 - - - 02 OUTPUT 0 1 0 0 out30
10 - - - 01 OUTPUT 0 1 0 0 out31
11 - - - 01 OUTPUT 0 1 0 0 out32
16 - - A -- OUTPUT 0 1 0 0 out33
72 - - A -- OUTPUT 0 1 0 0 out40
73 - - A -- OUTPUT 0 1 0 0 out41
78 - - - 24 OUTPUT 0 1 0 0 out42
79 - - - 24 OUTPUT 0 1 0 0 out43
67 - - B -- OUTPUT 0 1 0 0 out50
25 - - B -- OUTPUT 0 1 0 0 out51
23 - - B -- OUTPUT 0 1 0 0 out52
24 - - B -- OUTPUT 0 1 0 0 out53
80 - - - 23 OUTPUT 0 1 0 0 out60
81 - - - 22 OUTPUT 0 1 0 0 out61
83 - - - 13 OUTPUT 0 1 0 0 out62
3 - - - 12 OUTPUT 0 1 0 0 out63
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\2502144\02502144\jifei.rpt
jifei
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 21 AND2 0 2 0 1 |cnt10:u4|LPM_ADD_SUB:109|addcore:adder|:55
- 6 - B 21 AND2 0 3 0 1 |cnt10:u4|LPM_ADD_SUB:109|addcore:adder|:59
- 4 - B 11 DFFE 2 3 1 2 |cnt10:u4|cq3 (|cnt10:u4|:9)
- 4 - B 13 DFFE 2 3 1 3 |cnt10:u4|cq2 (|cnt10:u4|:10)
- 5 - B 21 DFFE 2 3 1 4 |cnt10:u4|cq1 (|cnt10:u4|:11)
- 2 - B 24 DFFE 2 2 1 5 |cnt10:u4|cq0 (|cnt10:u4|:12)
- 8 - B 21 OR2 0 4 0 4 |cnt10:u4|:80
- 1 - B 21 AND2 0 4 0 8 |cnt10:u4|:168
- 7 - B 02 OR2 2 2 0 2 |cnt16:u2|LPM_ADD_SUB:63|addcore:adder|pcarry1
- 7 - B 01 OR2 1 2 0 1 |cnt16:u2|LPM_ADD_SUB:63|addcore:adder|pcarry2
- 4 - B 02 OR2 s 2 1 0 1 |cnt16:u2|LPM_ADD_SUB:63|addcore:adder|~70~1
- 6 - B 01 OR2 s 1 1 0 1 |cnt16:u2|LPM_ADD_SUB:63|addcore:adder|~71~1
- 3 - B 01 DFFE 2 2 0 4 |cnt16:u2|aaa13 (|cnt16:u2|:20)
- 4 - B 01 DFFE 2 4 0 4 |cnt16:u2|aaa12 (|cnt16:u2|:21)
- 5 - B 02 DFFE 2 4 0 4 |cnt16:u2|aaa11 (|cnt16:u2|:22)
- 1 - B 02 DFFE 3 2 1 2 |cnt16:u2|aaa10 (|cnt16:u2|:23)
- 8 - B 01 OR2 1 3 0 1 |cnt16:u2|:73
- 3 - B 13 OR2 0 3 0 8 |cnt16:u2|:100
- 1 - B 01 AND2 0 3 1 1 |cnt16:u2|:149
- 5 - B 01 OR2 0 3 1 2 |cnt16:u2|:153
- 2 - B 01 OR2 0 3 1 2 |cnt16:u2|:159
- 5 - B 04 OR2 0 2 0 1 |cnt99:u3|LPM_ADD_SUB:196|addcore:adder|:67
- 7 - B 04 OR2 0 3 0 1 |cnt99:u3|LPM_ADD_SUB:196|addcore:adder|:68
- 1 - B 13 AND2 0 2 0 1 |cnt99:u3|LPM_ADD_SUB:434|addcore:adder|:55
- 5 - B 13 DFFE 2 3 1 2 |cnt99:u3|kk3 (|cnt99:u3|:20)
- 2 - B 05 DFFE 2 3 1 3 |cnt99:u3|kk2 (|cnt99:u3|:21)
- 1 - B 05 DFFE 2 3 1 4 |cnt99:u3|kk1 (|cnt99:u3|:22)
- 3 - B 05 DFFE 2 3 1 4 |cnt99:u3|kk0 (|cnt99:u3|:23)
- 4 - B 04 DFFE 4 2 1 3 |cnt99:u3|bb3 (|cnt99:u3|:24)
- 6 - B 04 DFFE 4 3 1 4 |cnt99:u3|bb2 (|cnt99:u3|:25)
- 3 - B 04 DFFE 4 3 1 5 |cnt99:u3|bb1 (|cnt99:u3|:26)
- 5 - B 05 DFFE 4 2 1 5 |cnt99:u3|bb0 (|cnt99:u3|:27)
- 2 - B 04 OR2 0 4 0 3 |cnt99:u3|:167
- 8 - B 04 OR2 0 4 0 1 |cnt99:u3|:223
- 1 - B 04 OR2 ! 0 4 0 5 |cnt99:u3|:391
- 4 - B 05 AND2 0 3 0 1 |cnt99:u3|:407
- 6 - B 05 OR2 s 0 3 0 4 |cnt99:u3|~495~1
- 2 - B 13 OR2 0 4 0 1 |cnt99:u3|:495
- 8 - B 05 OR2 0 4 0 1 |cnt99:u3|:501
- 7 - B 05 OR2 0 3 0 1 |cnt99:u3|:507
- 5 - C 23 OR2 0 2 0 1 |cnt99:u5|LPM_ADD_SUB:196|addcore:adder|:67
- 7 - C 23 OR2 0 3 0 1 |cnt99:u5|LPM_ADD_SUB:196|addcore:adder|:68
- 1 - B 12 AND2 0 2 0 1 |cnt99:u5|LPM_ADD_SUB:434|addcore:adder|:55
- 5 - B 10 DFFE 2 3 1 3 |cnt99:u5|kk3 (|cnt99:u5|:20)
- 4 - B 10 DFFE 2 3 1 3 |cnt99:u5|kk2 (|cnt99:u5|:21)
- 8 - B 02 DFFE 2 3 1 4 |cnt99:u5|kk1 (|cnt99:u5|:22)
- 1 - B 10 DFFE 2 3 1 4 |cnt99:u5|kk0 (|cnt99:u5|:23)
- 6 - C 23 DFFE 3 2 1 4 |cnt99:u5|bb3 (|cnt99:u5|:24)
- 2 - C 23 DFFE 3 3 1 5 |cnt99:u5|bb2 (|cnt99:u5|:25)
- 1 - C 23 DFFE 3 3 1 6 |cnt99:u5|bb1 (|cnt99:u5|:26)
- 3 - C 23 DFFE 3 2 1 6 |cnt99:u5|bb0 (|cnt99:u5|:27)
- 4 - C 23 OR2 0 4 0 3 |cnt99:u5|:167
- 8 - C 23 OR2 0 4 0 1 |cnt99:u5|:223
- 3 - B 02 OR2 ! 0 4 0 5 |cnt99:u5|:391
- 3 - B 10 OR2 ! 0 3 0 2 |cnt99:u5|:407
- 6 - B 10 OR2 s 0 3 0 4 |cnt99:u5|~495~1
- 8 - B 10 OR2 0 4 0 1 |cnt99:u5|:495
- 7 - B 10 OR2 0 4 0 1 |cnt99:u5|:501
- 2 - B 10 OR2 0 3 0 1 |cnt99:u5|:507
- 2 - B 02 OR2 s 0 3 0 1 |cnt99:u5|~533~1
- 6 - B 02 OR2 ! 0 4 0 4 |cnt99:u5|:533
- 7 - B 13 LCELL s 1 0 1 0 cout~1
- 4 - B 08 DFFE + 0 3 0 1 |Fenpin16:u1|tmp3 (|Fenpin16:u1|:5)
- 3 - B 08 DFFE + 0 2 0 2 |Fenpin16:u1|tmp2 (|Fenpin16:u1|:6)
- 2 - B 08 DFFE + 0 1 0 3 |Fenpin16:u1|tmp1 (|Fenpin16:u1|:7)
- 1 - B 08 DFFE + 0 0 0 4 |Fenpin16:u1|tmp0 (|Fenpin16:u1|:8)
- 6 - B 08 OR2 s 1 2 0 1 |Fenpin16:u1|~152~1
- 7 - B 08 OR2 s 1 2 0 1 |Fenpin16:u1|~152~2
- 5 - B 08 OR2 1 2 0 8 |Fenpin16:u1|:152
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\2502144\02502144\jifei.rpt
jifei
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 31/ 96( 32%) 19/ 48( 39%) 7/ 48( 14%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 1/ 48( 2%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\2502144\02502144\jifei.rpt
jifei
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 |cnt10:u4|:168
LCELL 8 |cnt16:u2|:100
LCELL 8 |Fenpin16:u1|:152
INPUT 4 clk
Device-Specific Information: f:\2502144\02502144\jifei.rpt
jifei
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 reset
Device-Specific Information: f:\2502144\02502144\jifei.rpt
jifei
** EQUATIONS **
aq0 : INPUT;
aq1 : INPUT;
aq2 : INPUT;
aq3 : INPUT;
clk : INPUT;
count0 : INPUT;
count1 : INPUT;
count2 : INPUT;
count3 : INPUT;
dd0 : INPUT;
dd1 : INPUT;
dd2 : INPUT;
dd3 : INPUT;
ko1 : INPUT;
ko2 : INPUT;
load : INPUT;
pg : INPUT;
reset : INPUT;
up_down : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC7_B13;
-- Node name is 'cout~1'
-- Equation name is 'cout~1', location is LC7_B13, type is buried.
-- synthesized logic cell
_LC7_B13 = LCELL( up_down);
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC3_B5;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
out11 = _LC1_B5;
-- Node name is 'out12'
-- Equation name is 'out12', type is output
out12 = _LC2_B5;
-- Node name is 'out13'
-- Equation name is 'out13', type is output
out13 = _LC5_B13;
-- Node name is 'out20'
-- Equation name is 'out20', type is output
out20 = _LC5_B5;
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