jifei.vhd

在本示例程序中

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jifei is
port(clk,reset,up_down,load,pg:in std_logic;
ko1,ko2:in std_logic;
count,dd,aq:in std_logic_vector(3 downto 0 );
cout:out std_logic;
out1,out2,out3,out4,out5,out6:out std_logic_vector(3 downto 0 ));
end;
architecture behav of jifei is
component Fenpin16
 port(a,b:in std_logic;
clk6:in std_logic;
clock6:out std_logic);
end component;
 component cnt10
    port(clk0,reset0,updown:in std_logic;
q:out std_logic_vector(3 downto 0 );
cout:out std_logic);
end component;
component cnt99
  port(clk2,reset2,updownp,load2:in std_logic;
d:in std_logic_vector(3 downto 0 );
enable:out std_logic;
y0,y1:out std_logic_vector(3 downto 0 );
ss,coutp:out std_logic);
end component;
component cnt16
  port(clk1,reset1,updownt,en:in std_logic;
sum:in std_logic_vector(3 downto 0 );
q1:out std_logic_vector(3 downto 0 );
yytt:out std_logic;
coutt:out std_logic);
end component;
signal vv,zz ,hh ,clock   :std_logic; 
begin
u1:Fenpin16 port map(a=>ko1,b=>ko2,clk6=>clk,clock6=>clock);
u2:cnt16 port map(clk1=>clock,reset1=>reset,updownt=>up_down,sum=>count,
                  q1=>out3,coutt=>vv,en=>hh,yytt=>cout);
u3:cnt99 port map(clk2=>vv,reset2=>reset,updownp=>up_down,load2=>load,
                  d=>dd,y0=>out2,y1=>out1);
u4:cnt10 port map(clk0=>clock,reset0=>reset,updown=>up_down,
                  q=>out6,cout=>zz);
u5:cnt99 port map(enable=>hh,clk2=>zz,reset2=>reset,updownp=>up_down,
                  y0=>out4,y1=>out5,d=>aq,load2=>pg);
end;