cnt99.vhd

来自「在本示例程序中」· VHDL 代码 · 共 67 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt99 is
    port(clk2,reset2,updownp,load2:in std_logic;
d:in std_logic_vector(3 downto 0 );
enable:out std_logic;
y0,y1:out std_logic_vector(3 downto 0 );
ss,coutp:out std_logic);
end;
architecture behav of cnt99 is
signal  bb,kk :std_logic_vector(3 downto 0);
signal q99:std_logic;
signal yout:std_logic_vector(7 downto 0);
begin
p1:   process(clk2,reset2,updownp)
begin
yout<=kk&bb;
if reset2='1' then bb<=(others=>'0');
elsif updownp='0' then bb<=bb;
elsif load2='1' then bb<=d;
elsif clk2'event and clk2='1' then
if bb<"1001" then bb<=bb+1;
else bb<=(others=>'0');
end if;
end if;
if bb="1001" then coutp<='1';
else coutp<='0';
end if;
y0<=bb;
end process;
p2:process(clk2,reset2,updownp)
begin
if reset2='1' then kk<=(others=>'0');
elsif updownp='0' then kk<=kk;
elsif clk2'event and clk2='1' then
if bb="1001" then 
if kk<"1001" then kk<=kk+1;
else kk<=(others=>'0');
end if;
end if;
end if;
if yout>="0011" then enable<='1';
else enable<='0';
end if;
if kk="1001" and bb="1001" then q99<='1';
   else q99<='0';
end if;
ss<=q99;
y1<=kk;
end process;
end behav;