cnt16.vhd

在本示例程序中

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt16 is
    port(clk1,reset1,updownt,en:in std_logic;
sum:in std_logic_vector(3 downto 0 );
q1:out std_logic_vector(3 downto 0 );
yytt:out std_logic;
coutt:out std_logic);
end;
architecture behav of cnt16 is
begin
process(clk1,reset1,updownt)
variable aaa1 :std_logic_vector(3 downto 0);
begin
yytt<=updownt;
if reset1='1' then aaa1:=(others=>'0');
elsif updownt='0' then aaa1:=aaa1;
elsif clk1'event and clk1='1' then
if en='1' then
aaa1:=aaa1+sum;
end if;
end if;
if aaa1>"1001" then coutt<='1';aaa1:=aaa1-"1010";
else aaa1:=aaa1;coutt<='0';
end if;
q1<=aaa1;
end process;
end behav;