a8251.vhd

8251 端口初始化 包含定义13个输入端口和9个输出端口

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;


ENTITY a8251 IS

	PORT 
	(
      clk			: IN  std_logic;
      reset    	: IN  std_logic;
      nWR     		: IN  std_logic;
      nRD     		: IN  std_logic;
      nCS     		: IN  std_logic;
      CnD     		: IN  std_logic;
      nDSR     	: IN  std_logic;
      nCTS     	: IN  std_logic;
      ExtSyncD		: IN  std_logic;
      nTxC     	: IN  std_logic;
      nRxC     	: IN  std_logic;
      rxd     		: IN  std_logic;
      din     		: IN  std_logic_vector(7 DOWNTO 0);

      txd       	: OUT std_logic;
      txrdy     	: OUT std_logic;
      txempty     : OUT std_logic;
      rxrdy     	: OUT std_logic;
      nDTR      	: OUT std_logic;
      nRTS      	: OUT std_logic;
      syn_brk     : OUT std_logic;
      nEN       	: OUT std_logic;
      dout     	: OUT std_logic_vector(7 DOWNTO 0)
	);
	                                              
END a8251;


ARCHITECTURE struct OF a8251 IS

	-------------------------------------------------------------------------------
	-- SIGNAL declarations
	-------------------------------------------------------------------------------
	SIGNAL	mode_cmplt			: std_logic;
	SIGNAL	error_resetn      : std_logic;
	SIGNAL	rx_resetn      	: std_logic;
	SIGNAL	tx_resetn       	: std_logic;
	SIGNAL	rx_read				: std_logic;
	SIGNAL	rx_enable         : std_logic;
	SIGNAL	tx_enable  			: std_logic;
	SIGNAL	break_enable  	 	: std_logic;  
	SIGNAL	hunt					: std_logic;
	SIGNAL	scs              	: std_logic;
	SIGNAL	esd					: std_logic;
	SIGNAL	b1						: std_logic;
	SIGNAL	b2  					: std_logic;
	SIGNAL	l1						: std_logic;
	SIGNAL	l2						: std_logic;
	SIGNAL	parity_en			: std_logic;
	SIGNAL	even_parity			: std_logic;
	SIGNAL	s1						: std_logic;
	SIGNAL	s2						: std_logic;
	SIGNAL	fe						: std_logic;
	SIGNAL	pe						: std_logic;
	SIGNAL	oe						: std_logic;
	SIGNAL	tran_en				: std_logic;
	SIGNAL	int_txrdy   	 	: std_logic;
	SIGNAL	int_rxrdy  	 		: std_logic;
	SIGNAL	int_txempty   	 	: std_logic;
	SIGNAL	int_syn_brk	 		: std_logic;
	SIGNAL  	sts_read				: std_logic;
	SIGNAL  	WriteAddrIn			: std_logic;
	SIGNAL	cycle_rec			: std_logic;
	SIGNAL	ext_nWR				: std_logic;

	SIGNAL	tx_sr_empty_n		: std_logic;

	SIGNAL	tx_fifo_wr_n		: std_logic;
	SIGNAL	tx_fifo_rd_n		: std_logic;
	SIGNAL	tx_fifo_din			: std_logic_vector(7 DOWNTO 0);
	SIGNAL	tx_fifo_ef_n		: std_logic;
	SIGNAL	tx_fifo_ff_n		: std_logic;
	SIGNAL	tx_fifo_dout		: std_logic_vector(7 DOWNTO 0);
		
	SIGNAL	status_data  		: std_logic_vector(7 DOWNTO 0);
	SIGNAL	mode_out     		: std_logic_vector(7 DOWNTO 0);
	SIGNAL	sync_char1      	: std_logic_vector(7 DOWNTO 0);
	SIGNAL	sync_char2      	: std_logic_vector(7 DOWNTO 0);
	SIGNAL	cmnd_out     		: std_logic_vector(7 DOWNTO 0);
	SIGNAL	rxreg          	: std_logic_vector(7 DOWNTO 0);
	SIGNAL	WriteDataIn			: std_logic_vector(7 DOWNTO 0);

	-------------------------------------------------------------------------------
	-- COMPONENT declarations
	-------------------------------------------------------------------------------
	COMPONENT proc
	 
		PORT 
		(
			ext_nWR     	: IN std_logic;
			nWR     			: IN std_logic;
	      nRD     			: IN std_logic;
	      ext_CnD     	: IN std_logic;
	      CnD     			: IN std_logic;
	      nCS     			: IN std_logic;
	      clr     			: IN std_logic;
	      clk       		: IN std_logic;
	      d    				: IN std_logic_vector(7 DOWNTO 0);
	      rxclk      		: IN std_logic;
	      txclk    		: IN std_logic;
	
			cycle_rec		: OUT std_logic;
			hunt				: OUT std_logic;
			error_resetn	: OUT std_logic;
			rx_resetn		: OUT std_logic;
			tx_resetn		: OUT std_logic;
			nRTS				: OUT std_logic;
			nDTR				: OUT std_logic;
			rx_enable		: OUT std_logic;
			tx_enable		: OUT std_logic;
			break_enable	: OUT std_logic;
      	mode_cmplt		: OUT std_logic;
      	sts_read      	: OUT std_logic;
      	tx_fifo_wr_n   : OUT std_logic;
      	rx_read     	: OUT std_logic;
      	mode_out     	: OUT std_logic_vector(7 DOWNTO 0);
      	sync_char1     : OUT std_logic_vector(7 DOWNTO 0);
      	sync_char2     : OUT std_logic_vector(7 DOWNTO 0)
		);
	                                                     
	END COMPONENT;
	
	
	COMPONENT rx
	 
		PORT 
		(
			reset          : IN  std_logic;   
	      mr           	: IN  std_logic;   
	      rx_en          : IN  std_logic;
	      rxclk       	: IN  std_logic;   
	      rxdata			: IN  std_logic;
	      sts_read      	: IN  std_logic;
	      mode_cmplt		: IN  std_logic;
	      hunt				: IN  std_logic;
	      scs            : IN  std_logic;
	      esd				: IN  std_logic;
	      ExtSyncD			: IN  std_logic;
	      er             : IN  std_logic;
	      b1					: IN  std_logic;
	      b2  				: IN  std_logic;
	      l1					: IN  std_logic;
	      l2					: IN  std_logic;
	      parity_en		: IN  std_logic;
			even_parity		: IN  std_logic;
	      s1					: IN  std_logic;
	      s2					: IN  std_logic;
	      rx_read			: IN  std_logic;
	      sync_char1   	: IN  std_logic_vector(7 DOWNTO 0);
	      sync_char2   	: IN  std_logic_vector(7 DOWNTO 0);
	      
	      fe					: OUT std_logic;
	      pe					: OUT std_logic;
	      oe					: OUT std_logic;
	      syn_brk			: OUT std_logic;
	      rxrdy				: OUT std_logic;
	      rxreg          : OUT std_logic_vector(7 DOWNTO 0)
		);
	
	END COMPONENT;
	
	
	COMPONENT tx
	 
		PORT 
		(
	      reset				: IN  std_logic;   
	      txclk				: IN  std_logic;   
	      tx_resetn		: IN  std_logic;
	      parity_en		: IN  std_logic;
	      parity_even		: IN  std_logic;
	      s1         		: IN  std_logic;
	      s2         		: IN  std_logic;
	      b1  				: IN  std_logic;
	      b2  				: IN  std_logic;
	      l1  				: IN  std_logic;
	      l2  				: IN  std_logic;
	      tx_en  			: IN  std_logic;
	      cts  				: IN  std_logic;
	      break_en   		: IN  std_logic;
      	tx_fifo_ef_n   : IN  std_logic;
	      txdin      		: IN  std_logic_vector(7 DOWNTO 0);
	      sync_char1     : IN  std_logic_vector(7 DOWNTO 0);
	      sync_char2     : IN  std_logic_vector(7 DOWNTO 0);
	
      	tx_fifo_rd_n	: OUT std_logic;
			tx_sr_empty_n	: OUT	std_logic;
			txdata			: OUT std_logic   
		);
	
	END COMPONENT;


	COMPONENT tx_fifo

		PORT 
		(
      	rst_n		: IN     std_logic;
			tx_rst_n	: IN		std_logic;
      	wr_n     : IN     std_logic;
			rd_clk	: IN		std_logic;
      	rd_n     : IN     std_logic;
      	d        : IN     std_logic_vector(7 DOWNTO 0);

      	ef_n     : OUT    std_logic;
      	ff_n     : OUT    std_logic;
      	q        : OUT    std_logic_vector(7 DOWNTO 0)
		);

	END COMPONENT;
	
	
	COMPONENT DataLatch
	
		PORT 
		(
			RESET			: IN	std_logic;
			DIN			: IN	std_logic_vector(7 DOWNTO 0);
			nWR			: IN	std_logic;
			nCS			: IN	std_logic;
	
			LatchedData	: INOUT	std_logic_vector(7 DOWNTO 0)
		);
	
	END COMPONENT;
	
	
	COMPONENT AddrLatch
	
		PORT 
		(
			RESET			: IN	std_logic;
			CnD			: IN	std_logic;
			nWR			: IN	std_logic;
			nCS			: IN	std_logic;
	
			LatchedAddr	: INOUT	std_logic
		);
	
	END COMPONENT;
	
	
	COMPONENT dout_mux
	
		PORT 
		(
	   	CnD     			: IN std_logic;
	   	rx_data      	: IN std_logic_vector(7 DOWNTO 0);
	   	status_data  	: IN std_logic_vector(7 DOWNTO 0);
	
	   	dout      		: OUT std_logic_vector(7 DOWNTO 0)
		);
	
	END COMPONENT;


	COMPONENT Wr_Ext
	
		PORT 
		(
			RESET			: IN		std_logic;
			nCS			: IN		std_logic;
			nWR			: IN		std_logic;
			cycle_rec	: IN		std_logic;

			ext_nWR		: INOUT	std_logic
		);
	
	END COMPONENT;

BEGIN

	-------------------------------------------------------------------------------
	-- Continuous Signal Assignments
	-------------------------------------------------------------------------------
	scs         	<= mode_out(7);
	esd				<= mode_out(6);
	b1					<= mode_out(0);
	b2  				<= mode_out(1);
	l1					<= mode_out(2);
	l2					<= mode_out(3);
	parity_en		<= mode_out(4);
	even_parity		<= mode_out(5);
	s1					<= mode_out(6);
	s2					<= mode_out(7);

	int_txrdy		<= tx_fifo_ff_n AND NOT nCTS AND tx_enable;
	txrdy				<= int_txrdy;

	int_txempty		<= tx_fifo_ff_n AND NOT tx_sr_empty_n;
	txempty			<= int_txempty;

	rxrdy				<= int_rxrdy;
	syn_brk			<= int_syn_brk;

	nEN				<= NOT ( (NOT nCS) AND (NOT nRD) );

	status_data		<= (NOT nDSR) & int_syn_brk & fe & oe & pe 
						& (tx_fifo_ff_n AND NOT tx_sr_empty_n) 
						& int_rxrdy & tx_fifo_ff_n;


	-------------------------------------------------------------------------------
	-- COMPONENT instantiations
	-------------------------------------------------------------------------------
	i_dout_mux : dout_mux
	PORT MAP
	(
		CnD     			=>	CnD,
      rx_data      	=>	rxreg,
      status_data  	=>	status_data,
      dout      		=>	dout
	);

	i_DataSync : DataLatch
	PORT MAP
	(
		RESET				=> RESET,
		DIN				=> DIN,
		nWR				=> nWR,
		nCS				=> nCS,
		LatchedData		=> WriteDataIn
	);

	i_AddrSync : AddrLatch
	PORT MAP
	(
		RESET				=> RESET,
		CnD				=> CnD,
		nWR				=> nWR,
		nCS				=> nCS,
		LatchedAddr		=> WriteAddrIn
	);

	i_Wr_Ext : Wr_Ext
	PORT MAP
	(
		RESET			=>	RESET,
		nCS			=> nCS,				
		nWR			=>	nWR,		
		cycle_rec	=>	cycle_rec,
		ext_nWR		=>	ext_nWR	
	);
          
	i_procintf : proc 
	PORT MAP
	(
      ext_nWR				=> ext_nWR,
      nWR     			   => nWR,
      nRD     			   => nRD,
      ext_CnD     		=> WriteAddrIn,
      CnD     			   => CnD,
      nCS     			   => nCS,
      clr     			   => reset,
      clk       		   => clk,
      d    				   => WriteDataIn,
      rxclk      		   => nRxC,
      txclk    			=> nTxC,

		cycle_rec			=> cycle_rec,		
		hunt					=> hunt,
		error_resetn		=> error_resetn,
		rx_resetn			=> rx_resetn,
		tx_resetn			=> tx_resetn,
		nRTS					=> nRTS,
		nDTR					=> nDTR,
		rx_enable			=> rx_enable,
		tx_enable			=> tx_enable,
		break_enable		=> break_enable,
      mode_cmplt			=> mode_cmplt,
      sts_read      		=> sts_read,
      tx_fifo_wr_n   	=> tx_fifo_wr_n,
      rx_read     		=> rx_read,
		mode_out				=> mode_out,
      sync_char1			=> sync_char1,     
      sync_char2     	=> sync_char2
	);                    

	i_rx : rx 
	PORT MAP
	(
        reset           => reset,
        mr           	=> rx_resetn,
        rx_en           => rx_enable,
        rxclk       		=> nRxC       ,
        rxdata				=> rxd   	  ,
        sts_read			=> sts_read	  ,
        mode_cmplt		=> mode_cmplt ,
        hunt				=> hunt		  ,
        scs             => scs        ,
        esd					=> esd		  ,
        ExtSyncD			=> ExtSyncD ,
        er              => error_resetn,
        b1					=> b1		  ,
        b2  				=> b2  		  ,
        l1					=> l1		  ,
        l2					=> l2		  ,
        parity_en			=> parity_en  ,
		even_parity			=> even_parity,
        s1					=> s1		  ,
        s2					=> s2		  ,
			rx_read			=> rx_read,
        sync_char1   	=> sync_char1      ,
        sync_char2   	=> sync_char2      ,
        fe					=> fe		  ,
        pe					=> pe		  ,
        oe					=> oe		  ,
        syn_brk			=> int_syn_brk,
        rxrdy				=> int_rxrdy,
        rxreg          	=> rxreg      
	);

	i_tx : tx
	PORT MAP
	(
		reset          => reset,
      txclk       	=> nTxC,
      tx_resetn      => tx_resetn,
      parity_en		=> parity_en,
      parity_even		=> even_parity,
      s1         		=> s1,
      s2         		=> s2,
      b1  				=> b1,
      b2  				=> b2,
      l1  				=> l1,
      l2  				=> l2,
      tx_en  			=> tx_enable,
      cts  				=> nCTS,
      break_en   		=> break_enable,
      tx_fifo_ef_n	=>	tx_fifo_ef_n,
      txdin      		=> tx_fifo_dout,
      sync_char1     => sync_char1,
      sync_char2     => sync_char2,

      tx_fifo_rd_n	=>	tx_fifo_rd_n,
      tx_sr_empty_n	=>	tx_sr_empty_n,
      txdata			=> txd		
	);

	i_tx_fifo : tx_fifo
	PORT MAP
	(
		rst_n				=> reset,
		tx_rst_n			=> tx_resetn,
      wr_n     		=> tx_fifo_wr_n,
		rd_clk			=> nTxC,
      rd_n     		=> tx_fifo_rd_n,
      d        		=> WriteDataIn,

      ef_n     		=> tx_fifo_ef_n,
      ff_n     		=> tx_fifo_ff_n,
      q        		=>	tx_fifo_dout
	); 


END struct;