cordic_top_struct.vhd

这是实现cordic算法的一些源程序

-- VHDL Entity HDesign_lib.cordic_top.symbol
--
-- Created:
--          by - gening.UNKNOWN (APWORKS)
--          at - 09:53:58 2006-04- 2
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY cordic_top IS
   PORT( 
      clk    : IN     std_logic;                       -- Clock, using rising_edge
      enable : IN     std_logic;                       -- The angle(theta) input indication, 1-theta is enabled,0-idle time
      reset  : IN     std_logic;                       -- Reset, 1-reset,0-normal. Suggest using asynchronous reset.
      theta  : IN     std_logic_vector (15 DOWNTO 0);  -- The input angle for calculation sin. It is normalized by pi/2.
      valid  : OUT    std_logic;                       -- The output sin value indication. 1-value is valid, 0-not ready.
      value  : OUT    std_logic_vector (15 DOWNTO 0)   -- The calculated sin for theta.
   );

-- Declarations

END cordic_top ;

--
-- VHDL Architecture HDesign_lib.cordic_top.struct
--
-- Created:
--          by - gening.UNKNOWN (APWORKS)
--          at - 09:53:59 2006-04- 2
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

--LIBRARY HDesign_lib;

ARCHITECTURE struct OF cordic_top IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL x_addend  : std_logic;
   SIGNAL x_addr0   : std_logic_vector(3 DOWNTO 0);
   SIGNAL x_addr1   : std_logic_vector(3 DOWNTO 0);
   SIGNAL x_data0   : std_logic;
   SIGNAL x_data1   : std_logic;
   SIGNAL x_op      : std_logic_vector(1 DOWNTO 0);
   SIGNAL x_re0     : std_logic;
   SIGNAL x_re1     : std_logic;
   SIGNAL x_value   : std_logic;
   SIGNAL x_we0     : std_logic;
   SIGNAL y_addend  : std_logic;
   SIGNAL y_addr0   : std_logic_vector(3 DOWNTO 0);
   SIGNAL y_addr1   : std_logic_vector(3 DOWNTO 0);
   SIGNAL y_data0   : std_logic;
   SIGNAL y_data1   : std_logic;
   SIGNAL y_op      : std_logic_vector(1 DOWNTO 0);
   SIGNAL y_re0     : std_logic;
   SIGNAL y_re1     : std_logic;
   SIGNAL y_value   : std_logic;
   SIGNAL y_we0     : std_logic;
   SIGNAL z_addr0   : std_logic_vector(3 DOWNTO 0);
   SIGNAL z_data0   : std_logic;
   SIGNAL z_data1   : std_logic;
   SIGNAL z_op      : std_logic_vector(1 DOWNTO 0);
   SIGNAL z_re0     : std_logic;
   SIGNAL z_re1     : std_logic;
   SIGNAL z_romdata : std_logic;  
   SIGNAL z_value   : std_logic;
   SIGNAL z_we0     : std_logic;


   -- Component Declarations
   COMPONENT cordic_add
   PORT (
      a   : IN     std_logic ;                      -- addend a
      b   : IN     std_logic ;                      -- addend b
      op  : IN     std_logic_vector ( 1 DOWNTO 0 ); -- operation, 11-Add,10-Subtract,01-Synchronous Reset,00-Idle
      sum : OUT    std_logic ;                      -- sum of a,b,carry
      clk : IN     std_logic                        -- Clock, using rising_edge
   );
   END COMPONENT;
   COMPONENT cordic_control
   PORT (
      clk       : IN     std_logic ;
      enable    : IN     std_logic ;                      -- theta indication
      reset     : IN     std_logic ;
      theta     : IN     std_logic_vector (15 DOWNTO 0);  -- input angle
      x_data1   : IN     std_logic ;                      -- Data from RAMX port 1, shifted of x
      x_value   : IN     std_logic ;                      -- add/sub result from adder
      y_data1   : IN     std_logic ;
      y_value   : IN     std_logic ;
      z_value   : IN     std_logic ;
      valid     : OUT    std_logic ;                      -- sin value valid indication
      value     : OUT    std_logic_vector (15 DOWNTO 0);  -- value for sin(theta)
      x_addend  : OUT    std_logic ;                      -- addend selected from x_data1 or 0
      x_addr0   : OUT    std_logic_vector ( 3 DOWNTO 0 ); -- address for RAMX port 0, original data
      x_addr1   : OUT    std_logic_vector ( 3 DOWNTO 0 ); -- address for RAMX port1, shifted data
      x_data0   : OUT    std_logic ;                      -- write back add/sub result
      x_op      : OUT    std_logic_vector ( 1 DOWNTO 0 ); -- operation control for adder
      x_re0     : OUT    std_logic ;                      -- read enable for RAMX port0
      x_re1     : OUT    std_logic ;                      -- read enable for RAMX port1
      x_we0     : OUT    std_logic ;                      -- write enable for RAMX port0, never write TO port1
      y_addend  : OUT    std_logic ;
      y_addr0   : OUT    std_logic_vector ( 3 DOWNTO 0 );
      y_addr1   : OUT    std_logic_vector ( 3 DOWNTO 0 );
      y_data0   : OUT    std_logic ;
      y_op      : OUT    std_logic_vector ( 1 DOWNTO 0 );
      y_re0     : OUT    std_logic ;
      y_re1     : OUT    std_logic ;
      y_we0     : OUT    std_logic ;
      z_addr0   : OUT    std_logic_vector ( 3 DOWNTO 0 );
      z_data0   : OUT    std_logic ;
      z_data1   : OUT    std_logic ;
      z_op      : OUT    std_logic_vector ( 1 DOWNTO 0 );
      z_re0     : OUT    std_logic ;
      z_romdata : OUT    std_logic ;                      -- stored rotated angle 
      z_we0     : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT cordic_dpram
   PORT (
      addr0 : IN     std_logic_vector ( 3 DOWNTO 0 ); -- R/W Address bus 0
      addr1 : IN     std_logic_vector ( 3 DOWNTO 0 ); -- R/W Address bus 1
      clk   : IN     std_logic ;                      -- clock
      re0   : IN     std_logic ;                      -- Read Enable for port0 
      re1   : IN     std_logic ;                      -- Read Enable for port1 
      we0   : IN     std_logic ;                      -- Write Enable  for port0 
      we1   : IN     std_logic ;                      -- Write Enable  for port1 
      data0 : INOUT  std_logic ;                      -- Bidirection Data bus 0 
      data1 : INOUT  std_logic                        -- Bidirection Data bus 1 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : cordic_add USE ENTITY cordic_add;   --HDesign_lib.
   FOR ALL : cordic_control USE ENTITY cordic_control;
   FOR ALL : cordic_dpram USE ENTITY cordic_dpram;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   Xadd : cordic_add
      PORT MAP (
         a   => x_data0,
         b   => x_addend,
         op  => x_op,
         sum => x_value,
         clk => clk
      );
   Yadd : cordic_add
      PORT MAP (
         a   => y_data0,
         b   => y_addend,
         op  => y_op,
         sum => y_value,
         clk => clk
      );
   Zadd : cordic_add
      PORT MAP (
         a   => z_data0,
         b   => z_romdata,
         op  => z_op,
         sum => z_value,
         clk => clk
      );
   Controller : cordic_control
      PORT MAP (
         clk       => clk,
         enable    => enable,
         reset     => reset,
         theta     => theta,
         x_data1   => x_data1,
         x_value   => x_value,
         y_data1   => y_data1,
         y_value   => y_value,
         z_value   => z_value,
         valid     => valid,
         value     => value,
         x_addend  => x_addend,
         x_addr0   => x_addr0,
         x_addr1   => x_addr1,
         x_data0   => x_data0,
         x_op      => x_op,
         x_re0     => x_re0,
         x_re1     => x_re1,
         x_we0     => x_we0,
         y_addend  => y_addend,
         y_addr0   => y_addr0,
         y_addr1   => y_addr1,
         y_data0   => y_data0,
         y_op      => y_op,
         y_re0     => y_re0,
         y_re1     => y_re1,
         y_we0     => y_we0,
         z_addr0   => z_addr0,
         z_data0   => z_data0,
         z_data1   => z_data1,
         z_op      => z_op,
         z_re0     => z_re0,
         z_romdata => z_romdata,
         z_we0     => z_we0
      );
   X : cordic_dpram
      PORT MAP (
         addr0 => x_addr0,
         addr1 => x_addr1,
         clk => clk,
         re0 => x_re0,
         re1 => x_re1,
         we0 => x_we0,
         data0 => x_data0,
         data1 => x_data1,
         we1 => '0'
      );
   Y : cordic_dpram
      PORT MAP (
         addr0 => y_addr0,
         addr1 => y_addr1,
         clk => clk,
         re0 => y_re0,
         re1 => y_re1,
         we0 => y_we0,
         data0 => y_data0,
         data1 => y_data1,
         we1 => '0'
      );
   Z : cordic_dpram
      PORT MAP (
         addr0 => z_addr0,
         clk => clk,
         re0 => z_re0,
         re1 => z_re1,
         we0 => z_we0,
         data0 => z_data0,
         data1 => z_data1,
         addr1 => "0000",
         we1 => '0'
      );

END struct;