cordic_add_rtl.vhd

这是实现cordic算法的一些源程序

--
-- VHDL Architecture HDesign_lib.cordic_add.rtl
--
-- Created:
--          by - gening.UNKNOWN (APWORKS)
--          at - 16:44:24 2006-03-23
--
-- using Mentor Graphics HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY cordic_add IS
   PORT( 
      a   : IN     std_logic;                        -- addend a
      b   : IN     std_logic;                        -- addend b
      op  : IN     std_logic_vector ( 1 DOWNTO 0 );  -- operation, 11-Add,10-Subtract,01-Synchronous Reset,00-Idle
      sum : OUT    std_logic;                        -- sum of a,b,carry
      clk : IN     std_logic                         -- Clock, using rising_edge
   );

-- Declarations

END cordic_add ;

--

ARCHITECTURE rtl OF cordic_add IS
signal carry : std_logic;
BEGIN
  main_prc: process(clk)
  variable result : std_logic_vector(1 downto 0);
  begin
    if rising_edge(clk) then
      case op is
      when "11" =>  --Add 
        result := ('0'& a) +  ('0'&b) + ('0'&carry);               
      when "10" =>  --Sub  
        result := ('0'&a) -  ('0'&b) - ('0'&carry);	                
      when "01" =>  --reset, clear carry
        result :="00";
      when "00" =>  --idle, keep unchanged
        result := carry  & a;
      when others => null;
      end case; 
      carry<=result(1);
      sum<=result(0);      
    end if;
  end process main_prc;
END ARCHITECTURE rtl;