cordic_dpram_beh.vhd

这是实现cordic算法的一些源程序

--
-- VHDL Architecture HDesign_lib.cordic_dpram.beh
--
-- Created:
--          by - gening.UNKNOWN (APWORKS)
--          at - 16:35:53 2006-03-23
--
-- using Mentor Graphics HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY cordic_dpram IS
   PORT( 
      addr0 : IN     std_logic_vector ( 3 DOWNTO 0 );  -- R/W Address bus 0 
      addr1 : IN     std_logic_vector ( 3 DOWNTO 0 );  -- R/W Address bus 1
      clk   : IN     std_logic;                        -- clock
      re0   : IN     std_logic;                        -- Read Enable for port0 
      re1   : IN     std_logic;                        -- Read Enable for port1
      we0   : IN     std_logic;                        -- Write Enable  for port0 
      we1   : IN     std_logic;                        -- Write Enable  for port1 
      data0 : INOUT  std_logic;                        -- Bidirection Data bus 0 
      data1 : INOUT  std_logic                         -- Bidirection Data bus 1
   );

-- Declarations

END cordic_dpram ;

--

ARCHITECTURE beh OF cordic_dpram IS
BEGIN
  main_prc: process(clk)
    variable bits: std_logic_vector(15 downto 0);
    variable uaddr0, uaddr1 : UNSIGNED(3 downto 0);
  begin
    if rising_edge(clk) then
      data0<='Z';
      data1<='Z';      
      uaddr0:=unsigned(addr0);
      uaddr1:=unsigned(addr1);
      if (we0='1') then			 --写ram 
        bits(to_integer(uaddr0)):=data0;
      end if;
      if (we1='1') then
        bits(to_integer(uaddr1)):=data1;
      end if;
      if (re0='1') then			 --读ram 
        data0<=bits(to_integer(uaddr0));
      end if;
      if (re1='1') then
        data1<=bits(to_integer(uaddr1));
      end if;					--可以在一个时钟周期内既读又写，读出来的数据为刚刚写入的数据； 
    end if;     
  end process;  
END ARCHITECTURE beh;