📄 1cordic_beh.mgf
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(_port (_internal y_we0 ~extieee.std_logic_1164.std_logic 0 42 (_entity (_out ))))
(_type (_internal ~std_logic_vector{3~downto~0}~1212 0 43 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
(_port (_internal z_addr0 ~std_logic_vector{3~downto~0}~1212 0 43 (_entity (_out ))))
(_port (_internal z_data0 ~extieee.std_logic_1164.std_logic 0 44 (_entity (_out ))))
(_port (_internal z_data1 ~extieee.std_logic_1164.std_logic 0 45 (_entity (_out ))))
(_type (_internal ~std_logic_vector{1~downto~0}~1214 0 46 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
(_port (_internal z_op ~std_logic_vector{1~downto~0}~1214 0 46 (_entity (_out ))))
(_port (_internal z_re0 ~extieee.std_logic_1164.std_logic 0 47 (_entity (_out ))))
(_port (_internal z_romdata ~extieee.std_logic_1164.std_logic 0 48 (_entity (_out ))))
(_port (_internal z_we0 ~extieee.std_logic_1164.std_logic 0 49 (_entity (_out ))))
(_type (_internal ~std_logic_vector{15~downto~0}~13 0 59 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_signal (_internal theta_shift_reg ~std_logic_vector{15~downto~0}~13 0 59 (_architecture (_uni ))))
(_signal (_internal value_shift_reg ~std_logic_vector{15~downto~0}~13 0 59 (_architecture (_uni ))))
(_signal (_internal zsign ~extieee.std_logic_1164.std_logic 0 60 (_architecture (_uni ))))
(_signal (_internal clear_addend ~extieee.std_logic_1164.std_logic 0 61 (_architecture (_uni ))))
(_type (_internal ~std_logic_vector{15~downto~0}~1316 0 62 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_constant (_internal initx ~std_logic_vector{15~downto~0}~1316 0 62 (_architecture (_string \"0100110110111010"\))))
(_type (_internal romword 0 63 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_type (_internal ~std_logic_vector{15~downto~0}~1319 0 64 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_type (_internal rom 0 64 (_array ~std_logic_vector{15~downto~0}~1319 ((_to (i 0)(i 11))))))
(_constant (_internal zrom rom 0 65 (_architecture ((((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 3)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2)))))))
(_type (_internal ~std_logic_vector{15{15~downto~1}~13 0 191 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 1))))))
(_type (_internal ~std_logic_vector{15{15~downto~1}~1323 0 241 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 1))))))
(_type (_internal ~std_logic_vector{15{15~downto~1}~1324 0 245 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 1))))))
(_process
(main_prc(_architecture 0 0 80 (_process (_target(12)(18)(17)(16)(20)(22)(14)(13)(9)(21)(26)(25)(24)(23)(15)(28)(27)(33)(32)(31)(30)(34)(35)(36)(37)))))
(line__265(_architecture 1 0 265 (_assignment (_simple)(_alias((value)(value_shift_reg)))(_target(10))(_sensitivity(35)))))
(line__266(_architecture 2 0 266 (_assignment (_simple)(_target(11))(_sensitivity(6)(37)))))
(line__267(_architecture 3 0 267 (_assignment (_simple)(_target(19))(_sensitivity(4)(37)))))
)
(_subprogram
(_internal write_ramx 4 0 82 (_architecture (_procedure )))
(_internal write_ramy 5 0 92 (_architecture (_procedure )))
(_internal write_ramz 6 0 102 (_architecture (_procedure )))
(_internal read_ramx 7 0 112 (_architecture (_procedure )))
(_internal read_ramy 8 0 122 (_architecture (_procedure )))
(_internal read_ramz 9 0 132 (_architecture (_procedure )))
(_internal default_all 10 0 139 (_architecture (_procedure )))
(_internal start_cordic 11 0 171 (_architecture (_procedure )))
(_internal load_theta 12 0 175 (_architecture (_procedure )))
(_internal calculate 13 0 196 (_architecture (_procedure )))
(_internal load_result 14 0 236 (_architecture (_procedure )))
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
(_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
(_type (_external ~extSTD.STANDARD.NATURAL (std STANDARD NATURAL)))
)
(_static
(2 2 2 2 )
(2 2 2 2 )
(2 2 )
(2 2 2 2 )
(2 2 2 2 )
(2 2 )
(2 2 2 2 )
(2 2 )
(2 3 )
(2 3 )
(2 3 )
)
(_model . beh 15 -1
)
)
V 000044 55 2604 1145801593626 beh(_unit VHDL (cordic_dpram 0 14 (beh 0 33 ))
(_version v33)
(_time 1145801593625 2006.04.23 22:13:13)
(_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_dpram_beh.vhd\))
(_use (std(standard))(ieee(numeric_std))(ieee(std_logic_1164)))
(_parameters dbg )
(_entity
(_time 1144462001469)
(_use )
)
(_object
(_type (_internal ~std_logic_vector{3~downto~0}~12 0 16 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
(_port (_internal addr0 ~std_logic_vector{3~downto~0}~12 0 16 (_entity (_in ))))
(_type (_internal ~std_logic_vector{3~downto~0}~122 0 17 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
(_port (_internal addr1 ~std_logic_vector{3~downto~0}~122 0 17 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 18 (_entity (_in )(_active)(_lastactive)(_event)(_lastevent)(_edge))))
(_port (_internal re0 ~extieee.std_logic_1164.std_logic 0 19 (_entity (_in ))))
(_port (_internal re1 ~extieee.std_logic_1164.std_logic 0 20 (_entity (_in ))))
(_port (_internal we0 ~extieee.std_logic_1164.std_logic 0 21 (_entity (_in ))))
(_port (_internal we1 ~extieee.std_logic_1164.std_logic 0 22 (_entity (_in ))))
(_port (_internal data0 ~extieee.std_logic_1164.std_logic 0 23 (_entity (_inout ))))
(_port (_internal data1 ~extieee.std_logic_1164.std_logic 0 24 (_entity (_inout ))))
(_type (_internal ~std_logic_vector{15~downto~0}~13 0 36 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_variable (_internal bits ~std_logic_vector{15~downto~0}~13 0 36 (_process 0 )))
(_type (_internal ~UNSIGNED{3~downto~0}~13 0 37 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
(_variable (_internal uaddr0 ~UNSIGNED{3~downto~0}~13 0 37 (_process 0 )))
(_variable (_internal uaddr1 ~UNSIGNED{3~downto~0}~13 0 37 (_process 0 )))
(_process
(main_prc(_architecture 0 0 35 (_process (_simple)(_target(7)(8))(_sensitivity(2))(_read(0)(3)(7)(6)(5)(1)(8)(4)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
(_type (_external ~extieee.numeric_std.UNSIGNED (ieee numeric_std UNSIGNED)))
)
(_model . beh 1 -1
)
)
V 000044 55 6010 1145801593891 beh(_unit VHDL (genmonitor 0 14 (beh 0 32 ))
(_version v33)
(_time 1145801593890 2006.04.23 22:13:13)
(_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/genmonitor_beh.vhd\))
(_use (std(standard))(std(textio))(ieee(std_logic_textio))(ieee(numeric_std))(ieee(std_logic_1164)))
(_parameters dbg )
(_entity
(_time 1144462001595)
(_use )
)
(_object
(_port (_internal valid ~extieee.std_logic_1164.std_logic 0 16 (_entity (_in ))))
(_type (_internal ~std_logic_vector{15~downto~0}~12 0 17 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_port (_internal value ~std_logic_vector{15~downto~0}~12 0 17 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 18 (_entity (_out ))))
(_port (_internal enable ~extieee.std_logic_1164.std_logic 0 19 (_entity (_out ))))
(_port (_internal reset ~extieee.std_logic_1164.std_logic 0 20 (_entity (_out ))))
(_type (_internal ~std_logic_vector{15~downto~0}~122 0 21 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_port (_internal theta ~std_logic_vector{15~downto~0}~122 0 21 (_entity (_out ))))
(_signal (_internal clki ~extieee.std_logic_1164.std_logic 0 33 (_architecture (_uni ((i 2))))))
(_signal (_internal clk1 ~extieee.std_logic_1164.std_logic 0 33 (_architecture (_uni ((i 2)))(_active)(_lastactive)(_event)(_lastevent)(_edge))))
(_type (_internal ~std_logic_vector{15~downto~0}~13 0 34 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
(_type (_internal words 0 34 (_array ~std_logic_vector{15~downto~0}~13 ((_to (i 1)(i 10))))))
(_constant (_internal theta_values words 0 35 (_architecture ((((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3)))(((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 3)))(((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3)))(((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3)))))))
(_constant (_internal ref_sinvalues words 0 47 (_architecture ((((i 2))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3)))(((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 2)))(((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 3))((i 2))((i 3))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2)))(((i 2))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3)))))))
(_variable (_internal log ~extstd.textio.LINE 0 76 (_process 3 )))
(_process
(line__60(_architecture 0 0 60 (_assignment (_simple)(_target(6))(_sensitivity(6)))))
(line__61(_architecture 1 0 61 (_assignment (_simple)(_alias((clk)(clki)))(_target(2))(_sensitivity(6)))))
(line__62(_architecture 2 0 62 (_assignment (_simple)(_alias((clk1)(clki)))(_target(7))(_sensitivity(6)))))
(line__63(_architecture 3 0 63 (_process (_target(5)(4)(3))(_read(0)(1)(7)))))
)
(_subprogram
(_internal cycles 4 0 64 (_architecture (_procedure )))
(_internal default_all 5 0 70 (_architecture (_procedure )))
(_external resolved (ieee std_logic_1164 0))
(_external WRITE (ieee std_logic_textio 8))
(_external WRITE (std textio 24))
(_external WRITELINE (std textio 17))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
(_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
(_type (_external ~extstd.textio.LINE (std textio LINE)))
(_type (_external ~extSTD.STANDARD.STRING (std STANDARD STRING)))
(_type (_external ~extSTD.STANDARD.CHARACTER (std STANDARD CHARACTER)))
(_type (_external ~extstd.textio.SIDE (std textio SIDE)))
(_type (_external ~extstd.textio.WIDTH (std textio WIDTH)))
(_type (_external ~extSTD.STANDARD.NATURAL (std STANDARD NATURAL)))
(_type (_external ~extstd.textio.TEXT (std textio TEXT)))
(_file (_external std.textio.output(std textio 1)))
)
(_static
(44 32 115 105 110 61 )
(44 32 114 101 102 61 )
(2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 )
)
(_model . beh 6 -1
)
)
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