1cordic_beh.mgf

这是实现cordic算法的一些源程序

    (_port (_internal we0 ~extieee.std_logic_1164.std_logic 0 21 (_entity (_in ))))
    (_port (_internal we1 ~extieee.std_logic_1164.std_logic 0 22 (_entity (_in ))))
    (_port (_internal data0 ~extieee.std_logic_1164.std_logic 0 23 (_entity (_inout ))))
    (_port (_internal data1 ~extieee.std_logic_1164.std_logic 0 24 (_entity (_inout ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~13 0 36 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_variable (_internal bits ~std_logic_vector{15~downto~0}~13 0 36 (_process 0 )))
    (_type (_internal ~UNSIGNED{3~downto~0}~13 0 37 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_variable (_internal uaddr0 ~UNSIGNED{3~downto~0}~13 0 37 (_process 0 )))
    (_variable (_internal uaddr1 ~UNSIGNED{3~downto~0}~13 0 37 (_process 0 )))
    (_process
      (main_prc(_architecture 0 0 35 (_process (_simple)(_target(7)(8))(_sensitivity(2))(_read(3)(7)(6)(0)(5)(1)(4)(8)))))
    )
    (_subprogram
      (_external resolved (ieee std_logic_1164 0))
    )
    (_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
    (_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
    (_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
    (_type (_external ~extieee.numeric_std.UNSIGNED (ieee numeric_std UNSIGNED)))
  )
  (_model . beh 1 -1
  )
)
I 000044 55 6010          1144462001672 beh
(_unit VHDL (genmonitor 0 14 (beh 0 32 ))
  (_version v33)
  (_time 1144462001671 2006.04.08 10:06:41)
  (_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/genmonitor_beh.vhd\))
  (_use (std(standard))(std(textio))(ieee(std_logic_textio))(ieee(numeric_std))(ieee(std_logic_1164)))
  (_parameters dbg )
  (_entity
    (_time 1144462001595)
    (_use )
  )
  (_object
    (_port (_internal valid ~extieee.std_logic_1164.std_logic 0 16 (_entity (_in ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~12 0 17 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_port (_internal value ~std_logic_vector{15~downto~0}~12 0 17 (_entity (_in ))))
    (_port (_internal clk ~extieee.std_logic_1164.std_logic 0 18 (_entity (_out ))))
    (_port (_internal enable ~extieee.std_logic_1164.std_logic 0 19 (_entity (_out ))))
    (_port (_internal reset ~extieee.std_logic_1164.std_logic 0 20 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~122 0 21 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_port (_internal theta ~std_logic_vector{15~downto~0}~122 0 21 (_entity (_out ))))
    (_signal (_internal clki ~extieee.std_logic_1164.std_logic 0 33 (_architecture (_uni ((i 2))))))
    (_signal (_internal clk1 ~extieee.std_logic_1164.std_logic 0 33 (_architecture (_uni ((i 2)))(_active)(_lastactive)(_event)(_lastevent)(_edge))))
    (_type (_internal ~std_logic_vector{15~downto~0}~13 0 34 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_type (_internal words 0 34 (_array ~std_logic_vector{15~downto~0}~13 ((_to (i 1)(i 10))))))
    (_constant (_internal theta_values words 0 35 (_architecture ((((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3)))(((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 3)))(((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3)))(((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3)))))))
    (_constant (_internal ref_sinvalues words 0 47 (_architecture ((((i 2))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3)))(((i 2))((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2)))(((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2))((i 2))((i 2)))(((i 2))((i 2))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 2)))(((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 3))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2)))(((i 2))((i 3))((i 2))((i 3))((i 3))((i 2))((i 3))((i 3))((i 3))((i 3))((i 2))((i 3))((i 2))((i 2))((i 3))((i 2)))(((i 2))((i 3))((i 3))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2))((i 2))((i 3))((i 2))((i 2)))(((i 2))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3))((i 3))((i 3))((i 2))((i 3))((i 3))((i 2))((i 3))((i 2))((i 3)))))))
    (_variable (_internal log ~extstd.textio.LINE 0 76 (_process 3 )))
    (_process
      (line__60(_architecture 0 0 60 (_assignment (_simple)(_target(6))(_sensitivity(6)))))
      (line__61(_architecture 1 0 61 (_assignment (_simple)(_alias((clk)(clki)))(_target(2))(_sensitivity(6)))))
      (line__62(_architecture 2 0 62 (_assignment (_simple)(_alias((clk1)(clki)))(_target(7))(_sensitivity(6)))))
      (line__63(_architecture 3 0 63 (_process (_target(4)(5)(3))(_read(0)(1)(7)))))
    )
    (_subprogram
      (_internal cycles 4 0 64 (_architecture (_procedure )))
      (_internal default_all 5 0 70 (_architecture (_procedure )))
      (_external resolved (ieee std_logic_1164 0))
      (_external WRITE (ieee std_logic_textio 8))
      (_external WRITE (std textio 24))
      (_external WRITELINE (std textio 17))
    )
    (_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
    (_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
    (_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
    (_type (_external ~extSTD.STANDARD.INTEGER (std STANDARD INTEGER)))
    (_type (_external ~extstd.textio.LINE (std textio LINE)))
    (_type (_external ~extSTD.STANDARD.STRING (std STANDARD STRING)))
    (_type (_external ~extSTD.STANDARD.CHARACTER (std STANDARD CHARACTER)))
    (_type (_external ~extstd.textio.SIDE (std textio SIDE)))
    (_type (_external ~extstd.textio.WIDTH (std textio WIDTH)))
    (_type (_external ~extSTD.STANDARD.NATURAL (std STANDARD NATURAL)))
    (_type (_external ~extstd.textio.TEXT (std textio TEXT)))
    (_file (_external std.textio.output(std textio 1)))
  )
  (_static
    (44 32 115 105 110 61 )
    (44 32 114 101 102 61 )
    (2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 )
  )
  (_model . beh 6 -1
  )
)
V 000044 55 1915          1145801592859 rtl
(_unit VHDL (cordic_add 0 14 (rtl 0 29 ))
  (_version v33)
  (_time 1145801592859 2006.04.23 22:13:12)
  (_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_add_rtl.vhd\))
  (_use (std(standard))(ieee(std_logic_unsigned))(ieee(std_logic_1164)))
  (_parameters dbg )
  (_entity
    (_time 1144462000922)
    (_use )
  )
  (_object
    (_port (_internal a ~extieee.std_logic_1164.std_logic 0 16 (_entity (_in ))))
    (_port (_internal b ~extieee.std_logic_1164.std_logic 0 17 (_entity (_in ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~12 0 18 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal op ~std_logic_vector{1~downto~0}~12 0 18 (_entity (_in ))))
    (_port (_internal sum ~extieee.std_logic_1164.std_logic 0 19 (_entity (_out ))))
    (_port (_internal clk ~extieee.std_logic_1164.std_logic 0 20 (_entity (_in )(_active)(_lastactive)(_event)(_lastevent)(_edge))))
    (_signal (_internal carry ~extieee.std_logic_1164.std_logic 0 30 (_architecture (_uni ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~13 0 33 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_variable (_internal result ~std_logic_vector{1~downto~0}~13 0 33 (_process 0 )))
    (_process
      (main_prc(_architecture 0 0 32 (_process (_simple)(_target(5)(3))(_sensitivity(4))(_read(5)(2)(1)(0)))))
    )
    (_subprogram
      (_external resolved (ieee std_logic_1164 0))
    )
    (_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
    (_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
    (_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
  )
  (_static
    (3 3 )
    (3 2 )
    (2 3 )
    (2 2 )
    (2 2 )
  )
  (_model . rtl 1 -1
  )
)
V 000044 55 9720          1145801593468 beh
(_unit VHDL (cordic_control 0 14 (beh 0 57 ))
  (_version v33)
  (_time 1145801593468 2006.04.23 22:13:13)
  (_source (\g:/2006春季课程/通信系统仿真与SOC集成-周祖成-2005春/1_A_作业/HDesign/HDesign_lib/hdl/cordic_control_rtl.vhd\))
  (_use (std(standard))(ieee(numeric_std))(ieee(std_logic_1164)))
  (_parameters dbg )
  (_entity
    (_time 1144462001266)
    (_use )
  )
  (_object
    (_port (_internal clk ~extieee.std_logic_1164.std_logic 0 16 (_entity (_in )(_active)(_lastactive)(_event)(_lastevent)(_edge))))
    (_port (_internal enable ~extieee.std_logic_1164.std_logic 0 17 (_entity (_in ))))
    (_port (_internal reset ~extieee.std_logic_1164.std_logic 0 18 (_entity (_in ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~12 0 19 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_port (_internal theta ~std_logic_vector{15~downto~0}~12 0 19 (_entity (_in ))))
    (_port (_internal x_data1 ~extieee.std_logic_1164.std_logic 0 20 (_entity (_in ))))
    (_port (_internal x_value ~extieee.std_logic_1164.std_logic 0 21 (_entity (_in ))))
    (_port (_internal y_data1 ~extieee.std_logic_1164.std_logic 0 22 (_entity (_in ))))
    (_port (_internal y_value ~extieee.std_logic_1164.std_logic 0 23 (_entity (_in ))))
    (_port (_internal z_value ~extieee.std_logic_1164.std_logic 0 24 (_entity (_in ))))
    (_port (_internal valid ~extieee.std_logic_1164.std_logic 0 25 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{15~downto~0}~122 0 26 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 15)(i 0))))))
    (_port (_internal value ~std_logic_vector{15~downto~0}~122 0 26 (_entity (_out ))))
    (_port (_internal x_addend ~extieee.std_logic_1164.std_logic 0 27 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~12 0 28 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal x_addr0 ~std_logic_vector{3~downto~0}~12 0 28 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~124 0 29 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal x_addr1 ~std_logic_vector{3~downto~0}~124 0 29 (_entity (_out ))))
    (_port (_internal x_data0 ~extieee.std_logic_1164.std_logic 0 30 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~12 0 31 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal x_op ~std_logic_vector{1~downto~0}~12 0 31 (_entity (_out ))))
    (_port (_internal x_re0 ~extieee.std_logic_1164.std_logic 0 32 (_entity (_out ))))
    (_port (_internal x_re1 ~extieee.std_logic_1164.std_logic 0 33 (_entity (_out ))))
    (_port (_internal x_we0 ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
    (_port (_internal y_addend ~extieee.std_logic_1164.std_logic 0 35 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~126 0 36 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal y_addr0 ~std_logic_vector{3~downto~0}~126 0 36 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{3~downto~0}~128 0 37 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 3)(i 0))))))
    (_port (_internal y_addr1 ~std_logic_vector{3~downto~0}~128 0 37 (_entity (_out ))))
    (_port (_internal y_data0 ~extieee.std_logic_1164.std_logic 0 38 (_entity (_out ))))
    (_type (_internal ~std_logic_vector{1~downto~0}~1210 0 39 (_array ~extieee.std_logic_1164.std_logic ((_downto (i 1)(i 0))))))
    (_port (_internal y_op ~std_logic_vector{1~downto~0}~1210 0 39 (_entity (_out ))))
    (_port (_internal y_re0 ~extieee.std_logic_1164.std_logic 0 40 (_entity (_out ))))
    (_port (_internal y_re1 ~extieee.std_logic_1164.std_logic 0 41 (_entity (_out ))))