📄 saomiao.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity saomiao is
port(clk :in std_logic;
mpx :in std_logic_vector(1 downto 0);
mpy :in std_logic_vector(3 downto 0);
mbx :in std_logic_vector(1 downto 0);
mby :in std_logic_vector(3 downto 0);
data :out std_logic_vector(7 downto 0);
v :buffer std_logic_vector(4 downto 0);
qin :in std_logic_vector(2 downto 0);
--q1 :buffer std_logic_vector(4 downto 0);
q2 :buffer std_logic_vector(2 downto 0);
e1 :out std_logic;
e2 :out std_logic);
end saomiao;
architecture behave of saomiao is
signal present_state :std_logic_vector(1 downto 0);
--signal q1 :std_logic_vector(4 downto 0);
--signal q2 :std_logic_vector(2 downto 0);
begin
process(present_state,clk)
-- variable temp: std_logic_vector(2 downto 0):=mbx(1 downto 0)&q2(0);
begin
if(rising_edge(clk))then
case present_state is
when"00"=>q2<="000";
if(v="11111")then
present_state<="01";
--q1<="00000";
v<=mpy&'1';
data<="00000000";
else
--q1<=q1+1;
v<=v+1;
present_state<="00";
end if;
when"01"=>--q1<="00000";
if(q2="111")then
present_state<="10";
q2<="000";
v<=mby&'0';
case mbx is
when "11"=>data<="10000000";
when "10"=>data<="00010000";
when "01"=>data<="00000010";
when others=>data<="00000000";
end case;
--data<="10000000" when mbx="11"else
-- "00010000"when mbx="10"else
-- "00000010"when mbx="01"else
-- "00000000";
else
v<=v-1;
if(q2(0)='1')then
if(mpx="11")then
data<="0000000"&qin(2);
else data<="00000000";
end if;
else
case mpx is
when "11"=>data<=qin(1 downto 0)&"000000";
when "10"=>data<="00"&qin(2 downto 0)&"000";
when "01"=>data<="00000"&qin(2 downto 0);
when others=>data<="00000000";
end case;
end if;
-- data<="0000000"&qin(2)when mbx="11"and q2(0)='0' else
-- qin(1 downto 0)&"000000"when mbx="11"and q2(0)='1' else
-- "00"&qin(2 downto 0)&"000"when q2(0)='1'and mbx="10" else
-- "00000"&qin(2 downto 0) when q2(0)='1'and mbx="01" else
-- "00000000";
q2<=q2+1;
present_state<="01";
end if;
when"10"=>present_state<="00";
---q1<="00000";
q2<="000";
v<="00000";
data<="00000000";
when others=>present_state<="00";
end case;
end if;
end process;
process(present_state)
begin
case present_state is
when "00"=>e1<='1';
e2<='0';
when"01"=>e1<='0';
e2<='1';
when others=>e1<='0';
e2<='0';
end case;
end process;
end behave;
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