automat.fit.qmsg

设计一个自动售货机控制程序

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 3.30 4 4 0 " "Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 4 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 26 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 26 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.083 ns register register " "Info: Estimated most critical path is register to register delay of 3.083 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cur_state.st2 1 REG LAB_X14_Y1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y1; Fanout = 4; REG Node = 'cur_state.st2'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { cur_state.st2 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.590 ns) 1.026 ns Select~618 2 COMB LAB_X13_Y1 1 " "Info: 2: + IC(0.436 ns) + CELL(0.590 ns) = 1.026 ns; Loc. = LAB_X13_Y1; Fanout = 1; COMB Node = 'Select~618'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.026 ns" { cur_state.st2 Select~618 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 1.690 ns Select~139 3 COMB LAB_X13_Y1 2 " "Info: 3: + IC(0.074 ns) + CELL(0.590 ns) = 1.690 ns; Loc. = LAB_X13_Y1; Fanout = 2; COMB Node = 'Select~139'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.664 ns" { Select~618 Select~139 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 2.354 ns next_state.st3 4 COMB LAB_X13_Y1 2 " "Info: 4: + IC(0.550 ns) + CELL(0.114 ns) = 2.354 ns; Loc. = LAB_X13_Y1; Fanout = 2; COMB Node = 'next_state.st3'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.664 ns" { Select~139 next_state.st3 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.614 ns) + CELL(0.115 ns) 3.083 ns cur_state.st3 5 REG LAB_X13_Y1 3 " "Info: 5: + IC(0.614 ns) + CELL(0.115 ns) = 3.083 ns; Loc. = LAB_X13_Y1; Fanout = 3; REG Node = 'cur_state.st3'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.729 ns" { next_state.st3 cur_state.st3 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.409 ns 45.70 % " "Info: Total cell delay = 1.409 ns ( 45.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.674 ns 54.30 % " "Info: Total interconnect delay = 1.674 ns ( 54.30 % )" {  } {  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "3.083 ns" { cur_state.st2 Select~618 Select~139 next_state.st3 cur_state.st3 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 16:37:51 2005 " "Info: Processing ended: Mon Nov 21 16:37:51 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}