automat.tan.qmsg

设计一个自动售货机控制程序

{ "Info" "ITDB_FULL_TPD_RESULT" "choice\[1\] give_change\[0\] 13.938 ns Longest " "Info: Longest tpd from source pin \"choice\[1\]\" to destination pin \"give_change\[0\]\" is 13.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns choice\[1\] 1 PIN PIN_52 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 7; PIN Node = 'choice\[1\]'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { choice[1] } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.400 ns) + CELL(0.292 ns) 7.167 ns Select~180 2 COMB LC_X14_Y1_N5 7 " "Info: 2: + IC(5.400 ns) + CELL(0.292 ns) = 7.167 ns; Loc. = LC_X14_Y1_N5; Fanout = 7; COMB Node = 'Select~180'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "5.692 ns" { choice[1] Select~180 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.143 ns) + CELL(0.590 ns) 8.900 ns Select~624 3 COMB LC_X12_Y1_N2 6 " "Info: 3: + IC(1.143 ns) + CELL(0.590 ns) = 8.900 ns; Loc. = LC_X12_Y1_N2; Fanout = 6; COMB Node = 'Select~624'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.733 ns" { Select~180 Select~624 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.046 ns) 9.946 ns give_change\[0\]\$latch 4 COMB LOOP LC_X12_Y1_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(1.046 ns) = 9.946 ns; Loc. = LC_X12_Y1_N6; Fanout = 2; COMB LOOP Node = 'give_change\[0\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "give_change\[0\]\$latch LC_X12_Y1_N6 " "Info: Loc. = LC_X12_Y1_N6; Node \"give_change\[0\]\$latch\"" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { give_change[0]$latch } "NODE_NAME" } "" } }  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { give_change[0]$latch } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.046 ns" { Select~624 give_change[0]$latch } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.884 ns) + CELL(2.108 ns) 13.938 ns give_change\[0\] 5 PIN PIN_42 0 " "Info: 5: + IC(1.884 ns) + CELL(2.108 ns) = 13.938 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'give_change\[0\]'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "3.992 ns" { give_change[0]$latch give_change[0] } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.511 ns 39.54 % " "Info: Total cell delay = 5.511 ns ( 39.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.427 ns 60.46 % " "Info: Total interconnect delay = 8.427 ns ( 60.46 % )" {  } {  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "13.938 ns" { choice[1] Select~180 Select~624 give_change[0]$latch give_change[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "13.938 ns" { choice[1] choice[1]~out0 Select~180 Select~624 give_change[0]$latch give_change[0] } { 0.000ns 0.000ns 5.400ns 1.143ns 0.000ns 1.884ns } { 0.000ns 1.475ns 0.292ns 0.590ns 1.046ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "cur_state.st4 din\[0\] clk -4.404 ns register " "Info: th for register \"cur_state.st4\" (data pin = \"din\[0\]\", clock pin = \"clk\") is -4.404 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { clk } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cur_state.st4 2 REG LC_X14_Y1_N7 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.434 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.322 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns din\[0\] 1 PIN PIN_51 10 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_51; Fanout = 10; PIN Node = 'din\[0\]'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { din[0] } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.111 ns) + CELL(0.292 ns) 6.878 ns Select~27 2 COMB LC_X14_Y1_N6 2 " "Info: 2: + IC(5.111 ns) + CELL(0.292 ns) = 6.878 ns; Loc. = LC_X14_Y1_N6; Fanout = 2; COMB Node = 'Select~27'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "5.403 ns" { din[0] Select~27 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.296 ns) 7.174 ns next_state.st4 3 COMB LOOP LC_X14_Y1_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.296 ns) = 7.174 ns; Loc. = LC_X14_Y1_N7; Fanout = 2; COMB LOOP Node = 'next_state.st4'" { { "Info" "ITDB_PART_OF_SCC" "next_state.st4 LC_X14_Y1_N7 " "Info: Loc. = LC_X14_Y1_N7; Node \"next_state.st4\"" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { next_state.st4 } "NODE_NAME" } "" } }  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { next_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.296 ns" { Select~27 next_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 7.322 ns cur_state.st4 4 REG LC_X14_Y1_N7 4 " "Info: 4: + IC(0.000 ns) + CELL(0.148 ns) = 7.322 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" {  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.148 ns" { next_state.st4 cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.211 ns 30.20 % " "Info: Total cell delay = 2.211 ns ( 30.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.111 ns 69.80 % " "Info: Total interconnect delay = 5.111 ns ( 69.80 % )" {  } {  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "7.322 ns" { din[0] Select~27 next_state.st4 cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "7.322 ns" { din[0] din[0]~out0 Select~27 next_state.st4 cur_state.st4 } { 0.000ns 0.000ns 5.111ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.292ns 0.296ns 0.148ns } } }  } 0}  } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "7.322 ns" { din[0] Select~27 next_state.st4 cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "7.322 ns" { din[0] din[0]~out0 Select~27 next_state.st4 cur_state.st4 } { 0.000ns 0.000ns 5.111ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.292ns 0.296ns 0.148ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 7 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 16:37:58 2005 " "Info: Processing ended: Mon Nov 21 16:37:58 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}