📄 automat.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "next_state.st5 " "Info: Node \"next_state.st5\"" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0} } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "next_state.st4 " "Info: Node \"next_state.st4\"" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0} } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 5 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cur_state.st4 register cur_state.st1 246.55 MHz 4.056 ns Internal " "Info: Clock \"clk\" has Internal fmax of 246.55 MHz between source register \"cur_state.st4\" and destination register \"cur_state.st1\" (period= 4.056 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.795 ns + Longest register register " "Info: + Longest register to register delay is 3.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cur_state.st4 1 REG LC_X14_Y1_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.590 ns) 1.783 ns Select~180 2 COMB LC_X14_Y1_N5 7 " "Info: 2: + IC(1.193 ns) + CELL(0.590 ns) = 1.783 ns; Loc. = LC_X14_Y1_N5; Fanout = 7; COMB Node = 'Select~180'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.783 ns" { cur_state.st4 Select~180 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.425 ns) 3.208 ns next_state.st1 3 COMB LOOP LC_X13_Y1_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(1.425 ns) = 3.208 ns; Loc. = LC_X13_Y1_N9; Fanout = 2; COMB LOOP Node = 'next_state.st1'" { { "Info" "ITDB_PART_OF_SCC" "next_state.st1 LC_X13_Y1_N9 " "Info: Loc. = LC_X13_Y1_N9; Node \"next_state.st1\"" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { next_state.st1 } "NODE_NAME" } "" } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { next_state.st1 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.425 ns" { Select~180 next_state.st1 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.115 ns) 3.795 ns cur_state.st1 4 REG LC_X13_Y1_N0 4 " "Info: 4: + IC(0.472 ns) + CELL(0.115 ns) = 3.795 ns; Loc. = LC_X13_Y1_N0; Fanout = 4; REG Node = 'cur_state.st1'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.587 ns" { next_state.st1 cur_state.st1 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.130 ns 56.13 % " "Info: Total cell delay = 2.130 ns ( 56.13 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.665 ns 43.87 % " "Info: Total interconnect delay = 1.665 ns ( 43.87 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "3.795 ns" { cur_state.st4 Select~180 next_state.st1 cur_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.795 ns" { cur_state.st4 Select~180 next_state.st1 cur_state.st1 } { 0.000ns 1.193ns 0.000ns 0.472ns } { 0.000ns 0.590ns 1.425ns 0.115ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { clk } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cur_state.st1 2 REG LC_X13_Y1_N0 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y1_N0; Fanout = 4; REG Node = 'cur_state.st1'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.434 ns" { clk cur_state.st1 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st1 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { clk } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cur_state.st4 2 REG LC_X14_Y1_N7 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.434 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st1 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "3.795 ns" { cur_state.st4 Select~180 next_state.st1 cur_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.795 ns" { cur_state.st4 Select~180 next_state.st1 cur_state.st1 } { 0.000ns 1.193ns 0.000ns 0.472ns } { 0.000ns 0.590ns 1.425ns 0.115ns } } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st1 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "cur_state.st4 choice\[1\] clk 7.579 ns register " "Info: tsu for register \"cur_state.st4\" (data pin = \"choice\[1\]\", clock pin = \"clk\") is 7.579 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.445 ns + Longest pin register " "Info: + Longest pin to register delay is 10.445 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns choice\[1\] 1 PIN PIN_52 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 7; PIN Node = 'choice\[1\]'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { choice[1] } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.391 ns) + CELL(0.590 ns) 7.456 ns Select~615 2 COMB LC_X13_Y1_N7 5 " "Info: 2: + IC(5.391 ns) + CELL(0.590 ns) = 7.456 ns; Loc. = LC_X13_Y1_N7; Fanout = 5; COMB Node = 'Select~615'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "5.981 ns" { choice[1] Select~615 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.590 ns) 8.783 ns Select~26 3 COMB LC_X12_Y1_N9 2 " "Info: 3: + IC(0.737 ns) + CELL(0.590 ns) = 8.783 ns; Loc. = LC_X12_Y1_N9; Fanout = 2; COMB Node = 'Select~26'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.327 ns" { Select~615 Select~26 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.514 ns) 10.297 ns next_state.st4 4 COMB LOOP LC_X14_Y1_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(1.514 ns) = 10.297 ns; Loc. = LC_X14_Y1_N7; Fanout = 2; COMB LOOP Node = 'next_state.st4'" { { "Info" "ITDB_PART_OF_SCC" "next_state.st4 LC_X14_Y1_N7 " "Info: Loc. = LC_X14_Y1_N7; Node \"next_state.st4\"" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { next_state.st4 } "NODE_NAME" } "" } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { next_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.514 ns" { Select~26 next_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.148 ns) 10.445 ns cur_state.st4 5 REG LC_X14_Y1_N7 4 " "Info: 5: + IC(0.000 ns) + CELL(0.148 ns) = 10.445 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "0.148 ns" { next_state.st4 cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.317 ns 41.33 % " "Info: Total cell delay = 4.317 ns ( 41.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.128 ns 58.67 % " "Info: Total interconnect delay = 6.128 ns ( 58.67 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "10.445 ns" { choice[1] Select~615 Select~26 next_state.st4 cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "10.445 ns" { choice[1] choice[1]~out0 Select~615 Select~26 next_state.st4 cur_state.st4 } { 0.000ns 0.000ns 5.391ns 0.737ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.590ns 0.590ns 1.514ns 0.148ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { clk } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cur_state.st4 2 REG LC_X14_Y1_N7 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.434 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "10.445 ns" { choice[1] Select~615 Select~26 next_state.st4 cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "10.445 ns" { choice[1] choice[1]~out0 Select~615 Select~26 next_state.st4 cur_state.st4 } { 0.000ns 0.000ns 5.391ns 0.737ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.590ns 0.590ns 1.514ns 0.148ns } } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk give_change\[0\] cur_state.st4 11.681 ns register " "Info: tco from clock \"clk\" to destination pin \"give_change\[0\]\" through register \"cur_state.st4\" is 11.681 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.903 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { clk } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns cur_state.st4 2 REG LC_X14_Y1_N7 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.434 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.554 ns + Longest register pin " "Info: + Longest register to pin delay is 8.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cur_state.st4 1 REG LC_X14_Y1_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { cur_state.st4 } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.590 ns) 1.783 ns Select~180 2 COMB LC_X14_Y1_N5 7 " "Info: 2: + IC(1.193 ns) + CELL(0.590 ns) = 1.783 ns; Loc. = LC_X14_Y1_N5; Fanout = 7; COMB Node = 'Select~180'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.783 ns" { cur_state.st4 Select~180 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.143 ns) + CELL(0.590 ns) 3.516 ns Select~624 3 COMB LC_X12_Y1_N2 6 " "Info: 3: + IC(1.143 ns) + CELL(0.590 ns) = 3.516 ns; Loc. = LC_X12_Y1_N2; Fanout = 6; COMB Node = 'Select~624'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.733 ns" { Select~180 Select~624 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.046 ns) 4.562 ns give_change\[0\]\$latch 4 COMB LOOP LC_X12_Y1_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(1.046 ns) = 4.562 ns; Loc. = LC_X12_Y1_N6; Fanout = 2; COMB LOOP Node = 'give_change\[0\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "give_change\[0\]\$latch LC_X12_Y1_N6 " "Info: Loc. = LC_X12_Y1_N6; Node \"give_change\[0\]\$latch\"" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { give_change[0]$latch } "NODE_NAME" } "" } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "" { give_change[0]$latch } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "1.046 ns" { Select~624 give_change[0]$latch } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.884 ns) + CELL(2.108 ns) 8.554 ns give_change\[0\] 5 PIN PIN_42 0 " "Info: 5: + IC(1.884 ns) + CELL(2.108 ns) = 8.554 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'give_change\[0\]'" { } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "3.992 ns" { give_change[0]$latch give_change[0] } "NODE_NAME" } "" } } { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.334 ns 50.67 % " "Info: Total cell delay = 4.334 ns ( 50.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.220 ns 49.33 % " "Info: Total interconnect delay = 4.220 ns ( 49.33 % )" { } { } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "8.554 ns" { cur_state.st4 Select~180 Select~624 give_change[0]$latch give_change[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "8.554 ns" { cur_state.st4 Select~180 Select~624 give_change[0]$latch give_change[0] } { 0.000ns 1.193ns 1.143ns 0.000ns 1.884ns } { 0.000ns 0.590ns 0.590ns 1.046ns 2.108ns } } } } 0} } { { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "2.903 ns" { clk cur_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.903 ns" { clk clk~out0 cur_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" "" { Report "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat_cmp.qrpt" Compiler "Automat" "UNKNOWN" "V1" "E:/我的文档/学习/设计论文/课程设计/Automat/db/Automat.quartus_db" { Floorplan "E:/我的文档/学习/设计论文/课程设计/Automat/" "" "8.554 ns" { cur_state.st4 Select~180 Select~624 give_change[0]$latch give_change[0] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "8.554 ns" { cur_state.st4 Select~180 Select~624 give_change[0]$latch give_change[0] } { 0.000ns 1.193ns 1.143ns 0.000ns 1.884ns } { 0.000ns 0.590ns 0.590ns 1.046ns 2.108ns } } } } 0}
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