automat.map.qmsg

设计一个自动售货机控制程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 21 16:37:37 2005 " "Info: Processing started: Mon Nov 21 16:37:37 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Automat -c Automat " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Automat -c Automat" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "automat.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file automat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Automat-behavior " "Info: Found design unit 1: Automat-behavior" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Automat " "Info: Found entity 1: Automat" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "automat.vhd(78) " "Info: VHDL Case Statement information at automat.vhd(78): OTHERS choice is never selected" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "commodity automat.vhd(24) " "Warning: VHDL Process Statement warning at automat.vhd(24): signal or variable \"commodity\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"commodity\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "give_change automat.vhd(24) " "Warning: VHDL Process Statement warning at automat.vhd(24): signal or variable \"give_change\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"give_change\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 24 0 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|Automat\|cur_state 6 0 " "Info: State machine \"\|Automat\|cur_state\" contains 6 states and 0 state bits" {  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Automat\|cur_state " "Info: Selected Auto state machine encoding method for state machine \"\|Automat\|cur_state\"" {  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Automat\|cur_state " "Info: Encoding result for state machine \"\|Automat\|cur_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cur_state.st5 " "Info: Encoded state bit \"cur_state.st5\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cur_state.st4 " "Info: Encoded state bit \"cur_state.st4\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cur_state.st3 " "Info: Encoded state bit \"cur_state.st3\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cur_state.st2 " "Info: Encoded state bit \"cur_state.st2\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cur_state.st1 " "Info: Encoded state bit \"cur_state.st1\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cur_state.st0 " "Info: Encoded state bit \"cur_state.st0\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Automat\|cur_state.st0 000000 " "Info: State \"\|Automat\|cur_state.st0\" uses code string \"000000\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Automat\|cur_state.st1 000011 " "Info: State \"\|Automat\|cur_state.st1\" uses code string \"000011\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Automat\|cur_state.st2 000101 " "Info: State \"\|Automat\|cur_state.st2\" uses code string \"000101\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Automat\|cur_state.st3 001001 " "Info: State \"\|Automat\|cur_state.st3\" uses code string \"001001\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Automat\|cur_state.st4 010001 " "Info: State \"\|Automat\|cur_state.st4\" uses code string \"010001\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Automat\|cur_state.st5 100001 " "Info: State \"\|Automat\|cur_state.st5\" uses code string \"100001\"" {  } { { "automat.vhd" "" { Text "E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "46 " "Info: Implemented 46 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "36 " "Info: Implemented 36 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 16:37:42 2005 " "Info: Processing ended: Mon Nov 21 16:37:42 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}