automat.map.rpt

设计一个自动售货机控制程序

+-----------------------------------------------+----+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 36    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 30    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 6     ;
; Number of cells with combinational logic only          ; 30    ;
; Number of cells with registers only                    ; 6     ;
; Number of cells with combinational logic and registers ; 0     ;
+--------------------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------+
; State Machine - |Automat|cur_state                                                                            ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+
; Name          ; cur_state.st5 ; cur_state.st4 ; cur_state.st3 ; cur_state.st2 ; cur_state.st1 ; cur_state.st0 ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+
; cur_state.st0 ; 0             ; 0             ; 0             ; 0             ; 0             ; 0             ;
; cur_state.st1 ; 0             ; 0             ; 0             ; 0             ; 1             ; 1             ;
; cur_state.st2 ; 0             ; 0             ; 0             ; 1             ; 0             ; 1             ;
; cur_state.st3 ; 0             ; 0             ; 1             ; 0             ; 0             ; 1             ;
; cur_state.st4 ; 0             ; 1             ; 0             ; 0             ; 0             ; 1             ;
; cur_state.st5 ; 1             ; 0             ; 0             ; 0             ; 0             ; 1             ;
+---------------+---------------+---------------+---------------+---------------+---------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
Automat


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |Automat                   ; 36 (36)     ; 6            ; 0           ; 10   ; 0            ; 30 (30)      ; 6 (6)             ; 0 (0)            ; 0 (0)           ; |Automat            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/我的文档/学习/设计论文/课程设计/Automat/Automat.map.eqn.


+-------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                      ;
+----------------------------------+-----------------+--------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                           ;
+----------------------------------+-----------------+--------------------------------------------------------+
; automat.vhd                      ; yes             ; E:/我的文档/学习/设计论文/课程设计/Automat/automat.vhd ;
+----------------------------------+-----------------+--------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 36        ;
; Total combinational functions   ; 30        ;
; Total 4-input functions         ; 18        ;
; Total 3-input functions         ; 9         ;
; Total 2-input functions         ; 3         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 6         ;
; I/O pins                        ; 10        ;
; Maximum fan-out node            ; din[1]    ;
; Maximum fan-out                 ; 10        ;
; Total fan-out                   ; 127       ;
; Average fan-out                 ; 2.76      ;
+---------------------------------+-----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Nov 21 16:37:37 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Automat -c Automat
Info: Found 2 design units, including 1 entities, in source file automat.vhd
    Info: Found design unit 1: Automat-behavior
    Info: Found entity 1: Automat
Info: VHDL Case Statement information at automat.vhd(78): OTHERS choice is never selected
Warning: VHDL Process Statement warning at automat.vhd(24): signal or variable "commodity" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "commodity" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at automat.vhd(24): signal or variable "give_change" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "give_change" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: State machine "|Automat|cur_state" contains 6 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|Automat|cur_state"
Info: Encoding result for state machine "|Automat|cur_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "cur_state.st5"
        Info: Encoded state bit "cur_state.st4"
        Info: Encoded state bit "cur_state.st3"
        Info: Encoded state bit "cur_state.st2"
        Info: Encoded state bit "cur_state.st1"
        Info: Encoded state bit "cur_state.st0"
    Info: State "|Automat|cur_state.st0" uses code string "000000"
    Info: State "|Automat|cur_state.st1" uses code string "000011"
    Info: State "|Automat|cur_state.st2" uses code string "000101"
    Info: State "|Automat|cur_state.st3" uses code string "001001"
    Info: State "|Automat|cur_state.st4" uses code string "010001"
    Info: State "|Automat|cur_state.st5" uses code string "100001"
Info: Implemented 46 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 4 output pins
    Info: Implemented 36 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Nov 21 16:37:42 2005
    Info: Elapsed time: 00:00:05