📄 automat.fit.rpt
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; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 11 / 16,320 ( < 1 % ) ;
; Direct links ; 7 / 21,944 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; LAB clocks ; 2 / 240 ( < 1 % ) ;
; LUT chains ; 3 / 5,382 ( < 1 % ) ;
; Local interconnects ; 41 / 21,944 ( < 1 % ) ;
; M4K buffers ; 0 / 720 ( 0 % ) ;
; R4s ; 19 / 14,640 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 7.75) ; Number of LABs (Total = 4) ;
+--------------------------------------------+-----------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 3 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 4) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 2 ;
; 1 Clock ; 2 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 9.00) ; Number of LABs (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 4) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 8.25) ; Number of LABs (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Mon Nov 21 16:37:44 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off Automat -c Automat
Info: Selected device EP1C6T144C8 for design "Automat"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C3T144C8 is compatible
Info: No exact pin location assignment(s) for 10 pins of 10 total pins
Info: Pin commodity[1] not assigned to an exact location on the device
Info: Pin commodity[0] not assigned to an exact location on the device
Info: Pin give_change[1] not assigned to an exact location on the device
Info: Pin give_change[0] not assigned to an exact location on the device
Info: Pin choice[1] not assigned to an exact location on the device
Info: Pin choice[0] not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin rst not assigned to an exact location on the device
Info: Pin din[1] not assigned to an exact location on the device
Info: Pin din[0] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Automatically promoted signal "rst" to use Global clock in PIN 16
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 4 input, 4 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used -- 18 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 26 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 24 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 26 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 3.083 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y1; Fanout = 4; REG Node = 'cur_state.st2'
Info: 2: + IC(0.436 ns) + CELL(0.590 ns) = 1.026 ns; Loc. = LAB_X13_Y1; Fanout = 1; COMB Node = 'Select~618'
Info: 3: + IC(0.074 ns) + CELL(0.590 ns) = 1.690 ns; Loc. = LAB_X13_Y1; Fanout = 2; COMB Node = 'Select~139'
Info: 4: + IC(0.550 ns) + CELL(0.114 ns) = 2.354 ns; Loc. = LAB_X13_Y1; Fanout = 2; COMB Node = 'next_state.st3'
Info: 5: + IC(0.614 ns) + CELL(0.115 ns) = 3.083 ns; Loc. = LAB_X13_Y1; Fanout = 3; REG Node = 'cur_state.st3'
Info: Total cell delay = 1.409 ns ( 45.70 % )
Info: Total interconnect delay = 1.674 ns ( 54.30 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Nov 21 16:37:51 2005
Info: Elapsed time: 00:00:07
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