automat.tan.rpt

设计一个自动售货机控制程序

; N/A   ; None         ; 9.437 ns   ; cur_state.st3 ; give_change[0] ; clk        ;
; N/A   ; None         ; 9.153 ns   ; cur_state.st3 ; give_change[1] ; clk        ;
; N/A   ; None         ; 8.937 ns   ; cur_state.st3 ; commodity[0]   ; clk        ;
; N/A   ; None         ; 8.831 ns   ; cur_state.st3 ; commodity[1]   ; clk        ;
+-------+--------------+------------+---------------+----------------+------------+


+--------------------------------------------------------------------------+
; tpd                                                                      ;
+-------+-------------------+-----------------+-----------+----------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From      ; To             ;
+-------+-------------------+-----------------+-----------+----------------+
; N/A   ; None              ; 13.938 ns       ; choice[1] ; give_change[0] ;
; N/A   ; None              ; 13.714 ns       ; choice[0] ; give_change[0] ;
; N/A   ; None              ; 13.654 ns       ; choice[1] ; give_change[1] ;
; N/A   ; None              ; 13.430 ns       ; choice[0] ; give_change[1] ;
; N/A   ; None              ; 13.332 ns       ; choice[1] ; commodity[1]   ;
; N/A   ; None              ; 13.108 ns       ; choice[0] ; commodity[1]   ;
; N/A   ; None              ; 12.899 ns       ; choice[1] ; commodity[0]   ;
; N/A   ; None              ; 12.768 ns       ; choice[0] ; commodity[0]   ;
+-------+-------------------+-----------------+-----------+----------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+-----------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To            ; To Clock ;
+---------------+-------------+-----------+-----------+---------------+----------+
; N/A           ; None        ; -4.404 ns ; din[0]    ; cur_state.st4 ; clk      ;
; N/A           ; None        ; -4.563 ns ; din[1]    ; cur_state.st4 ; clk      ;
; N/A           ; None        ; -4.739 ns ; din[0]    ; cur_state.st1 ; clk      ;
; N/A           ; None        ; -5.144 ns ; din[1]    ; cur_state.st1 ; clk      ;
; N/A           ; None        ; -5.281 ns ; din[1]    ; cur_state.st2 ; clk      ;
; N/A           ; None        ; -5.283 ns ; din[1]    ; cur_state.st5 ; clk      ;
; N/A           ; None        ; -5.303 ns ; choice[0] ; cur_state.st2 ; clk      ;
; N/A           ; None        ; -5.397 ns ; din[0]    ; cur_state.st5 ; clk      ;
; N/A           ; None        ; -5.398 ns ; din[0]    ; cur_state.st2 ; clk      ;
; N/A           ; None        ; -5.405 ns ; choice[1] ; cur_state.st2 ; clk      ;
; N/A           ; None        ; -5.437 ns ; din[0]    ; cur_state.st0 ; clk      ;
; N/A           ; None        ; -5.618 ns ; choice[0] ; cur_state.st5 ; clk      ;
; N/A           ; None        ; -5.720 ns ; choice[1] ; cur_state.st5 ; clk      ;
; N/A           ; None        ; -5.741 ns ; din[0]    ; cur_state.st3 ; clk      ;
; N/A           ; None        ; -5.833 ns ; din[1]    ; cur_state.st3 ; clk      ;
; N/A           ; None        ; -5.849 ns ; din[1]    ; cur_state.st0 ; clk      ;
; N/A           ; None        ; -5.895 ns ; choice[0] ; cur_state.st4 ; clk      ;
; N/A           ; None        ; -6.037 ns ; choice[0] ; cur_state.st1 ; clk      ;
; N/A           ; None        ; -6.094 ns ; choice[0] ; cur_state.st0 ; clk      ;
; N/A           ; None        ; -6.119 ns ; choice[1] ; cur_state.st4 ; clk      ;
; N/A           ; None        ; -6.196 ns ; choice[1] ; cur_state.st0 ; clk      ;
; N/A           ; None        ; -6.261 ns ; choice[1] ; cur_state.st1 ; clk      ;
; N/A           ; None        ; -6.462 ns ; choice[0] ; cur_state.st3 ; clk      ;
; N/A           ; None        ; -6.564 ns ; choice[1] ; cur_state.st3 ; clk      ;
+---------------+-------------+-----------+-----------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Nov 21 16:37:57 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Automat -c Automat --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "next_state.st4" is a latch
    Warning: Node "commodity[1]$latch" is a latch
    Warning: Node "give_change[1]$latch" is a latch
    Warning: Node "give_change[0]$latch" is a latch
    Warning: Node "next_state.st1" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "next_state.st1"
Info: Found combinational loop of 1 nodes
    Info: Node "next_state.st0"
Info: Found combinational loop of 1 nodes
    Info: Node "next_state.st2"
Info: Found combinational loop of 1 nodes
    Info: Node "give_change[0]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "give_change[1]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "commodity[0]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "commodity[1]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "next_state.st3"
Info: Found combinational loop of 1 nodes
    Info: Node "next_state.st5"
Info: Found combinational loop of 1 nodes
    Info: Node "next_state.st4"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 246.55 MHz between source register "cur_state.st4" and destination register "cur_state.st1" (period= 4.056 ns)
    Info: + Longest register to register delay is 3.795 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: 2: + IC(1.193 ns) + CELL(0.590 ns) = 1.783 ns; Loc. = LC_X14_Y1_N5; Fanout = 7; COMB Node = 'Select~180'
        Info: 3: + IC(0.000 ns) + CELL(1.425 ns) = 3.208 ns; Loc. = LC_X13_Y1_N9; Fanout = 2; COMB LOOP Node = 'next_state.st1'
            Info: Loc. = LC_X13_Y1_N9; Node "next_state.st1"
        Info: 4: + IC(0.472 ns) + CELL(0.115 ns) = 3.795 ns; Loc. = LC_X13_Y1_N0; Fanout = 4; REG Node = 'cur_state.st1'
        Info: Total cell delay = 2.130 ns ( 56.13 % )
        Info: Total interconnect delay = 1.665 ns ( 43.87 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.903 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y1_N0; Fanout = 4; REG Node = 'cur_state.st1'
            Info: Total cell delay = 2.180 ns ( 75.09 % )
            Info: Total interconnect delay = 0.723 ns ( 24.91 % )
        Info: - Longest clock path from clock "clk" to source register is 2.903 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
            Info: Total cell delay = 2.180 ns ( 75.09 % )
            Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "cur_state.st4" (data pin = "choice[1]", clock pin = "clk") is 7.579 ns
    Info: + Longest pin to register delay is 10.445 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 7; PIN Node = 'choice[1]'
        Info: 2: + IC(5.391 ns) + CELL(0.590 ns) = 7.456 ns; Loc. = LC_X13_Y1_N7; Fanout = 5; COMB Node = 'Select~615'
        Info: 3: + IC(0.737 ns) + CELL(0.590 ns) = 8.783 ns; Loc. = LC_X12_Y1_N9; Fanout = 2; COMB Node = 'Select~26'
        Info: 4: + IC(0.000 ns) + CELL(1.514 ns) = 10.297 ns; Loc. = LC_X14_Y1_N7; Fanout = 2; COMB LOOP Node = 'next_state.st4'
            Info: Loc. = LC_X14_Y1_N7; Node "next_state.st4"
        Info: 5: + IC(0.000 ns) + CELL(0.148 ns) = 10.445 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: Total cell delay = 4.317 ns ( 41.33 % )
        Info: Total interconnect delay = 6.128 ns ( 58.67 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "clk" to destination pin "give_change[0]" through register "cur_state.st4" is 11.681 ns
    Info: + Longest clock path from clock "clk" to source register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 8.554 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: 2: + IC(1.193 ns) + CELL(0.590 ns) = 1.783 ns; Loc. = LC_X14_Y1_N5; Fanout = 7; COMB Node = 'Select~180'
        Info: 3: + IC(1.143 ns) + CELL(0.590 ns) = 3.516 ns; Loc. = LC_X12_Y1_N2; Fanout = 6; COMB Node = 'Select~624'
        Info: 4: + IC(0.000 ns) + CELL(1.046 ns) = 4.562 ns; Loc. = LC_X12_Y1_N6; Fanout = 2; COMB LOOP Node = 'give_change[0]$latch'
            Info: Loc. = LC_X12_Y1_N6; Node "give_change[0]$latch"
        Info: 5: + IC(1.884 ns) + CELL(2.108 ns) = 8.554 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'give_change[0]'
        Info: Total cell delay = 4.334 ns ( 50.67 % )
        Info: Total interconnect delay = 4.220 ns ( 49.33 % )
Info: Longest tpd from source pin "choice[1]" to destination pin "give_change[0]" is 13.938 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 7; PIN Node = 'choice[1]'
    Info: 2: + IC(5.400 ns) + CELL(0.292 ns) = 7.167 ns; Loc. = LC_X14_Y1_N5; Fanout = 7; COMB Node = 'Select~180'
    Info: 3: + IC(1.143 ns) + CELL(0.590 ns) = 8.900 ns; Loc. = LC_X12_Y1_N2; Fanout = 6; COMB Node = 'Select~624'
    Info: 4: + IC(0.000 ns) + CELL(1.046 ns) = 9.946 ns; Loc. = LC_X12_Y1_N6; Fanout = 2; COMB LOOP Node = 'give_change[0]$latch'
        Info: Loc. = LC_X12_Y1_N6; Node "give_change[0]$latch"
    Info: 5: + IC(1.884 ns) + CELL(2.108 ns) = 13.938 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'give_change[0]'
    Info: Total cell delay = 5.511 ns ( 39.54 % )
    Info: Total interconnect delay = 8.427 ns ( 60.46 % )
Info: th for register "cur_state.st4" (data pin = "din[0]", clock pin = "clk") is -4.404 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.322 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_51; Fanout = 10; PIN Node = 'din[0]'
        Info: 2: + IC(5.111 ns) + CELL(0.292 ns) = 6.878 ns; Loc. = LC_X14_Y1_N6; Fanout = 2; COMB Node = 'Select~27'
        Info: 3: + IC(0.000 ns) + CELL(0.296 ns) = 7.174 ns; Loc. = LC_X14_Y1_N7; Fanout = 2; COMB LOOP Node = 'next_state.st4'
            Info: Loc. = LC_X14_Y1_N7; Node "next_state.st4"
        Info: 4: + IC(0.000 ns) + CELL(0.148 ns) = 7.322 ns; Loc. = LC_X14_Y1_N7; Fanout = 4; REG Node = 'cur_state.st4'
        Info: Total cell delay = 2.211 ns ( 30.20 % )
        Info: Total interconnect delay = 5.111 ns ( 69.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 7 warnings
    Info: Processing ended: Mon Nov 21 16:37:58 2005
    Info: Elapsed time: 00:00:02