📄 automat.tan.rpt
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Timing Analyzer report for Automat
Mon Nov 21 16:37:58 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+---------------+----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------+----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 7.579 ns ; choice[1] ; cur_state.st4 ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 11.681 ns ; cur_state.st4 ; give_change[0] ; clk ; ; 0 ;
; Worst-case tpd ; N/A ; None ; 13.938 ns ; choice[1] ; give_change[0] ; ; ; 0 ;
; Worst-case th ; N/A ; None ; -4.404 ns ; din[0] ; cur_state.st4 ; ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 246.55 MHz ( period = 4.056 ns ) ; cur_state.st4 ; cur_state.st1 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+---------------+----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minumum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Clock Analysis Only ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off clear and preset signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Do Min/Max analysis using Rise/Fall delays ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Use Clock Latency for PLL offset ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 246.55 MHz ( period = 4.056 ns ) ; cur_state.st4 ; cur_state.st1 ; clk ; clk ; None ; None ; 3.795 ns ;
; N/A ; 247.22 MHz ( period = 4.045 ns ) ; cur_state.st2 ; cur_state.st2 ; clk ; clk ; None ; None ; 3.784 ns ;
; N/A ; 255.49 MHz ( period = 3.914 ns ) ; cur_state.st4 ; cur_state.st4 ; clk ; clk ; None ; None ; 3.653 ns ;
; N/A ; 261.23 MHz ( period = 3.828 ns ) ; cur_state.st1 ; cur_state.st1 ; clk ; clk ; None ; None ; 3.567 ns ;
; N/A ; 263.92 MHz ( period = 3.789 ns ) ; cur_state.st4 ; cur_state.st3 ; clk ; clk ; None ; None ; 3.528 ns ;
; N/A ; 270.05 MHz ( period = 3.703 ns ) ; cur_state.st4 ; cur_state.st0 ; clk ; clk ; None ; None ; 3.442 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st3 ; cur_state.st4 ; clk ; clk ; None ; None ; 3.367 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st0 ; cur_state.st2 ; clk ; clk ; None ; None ; 3.309 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st5 ; cur_state.st3 ; clk ; clk ; None ; None ; 3.309 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st5 ; cur_state.st1 ; clk ; clk ; None ; None ; 3.298 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st5 ; cur_state.st0 ; clk ; clk ; None ; None ; 3.223 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st5 ; cur_state.st4 ; clk ; clk ; None ; None ; 3.156 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st2 ; cur_state.st3 ; clk ; clk ; None ; None ; 2.984 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st1 ; cur_state.st2 ; clk ; clk ; None ; None ; 2.734 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st3 ; cur_state.st3 ; clk ; clk ; None ; None ; 2.710 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st1 ; cur_state.st0 ; clk ; clk ; None ; None ; 2.621 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st1 ; cur_state.st3 ; clk ; clk ; None ; None ; 2.484 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st0 ; cur_state.st0 ; clk ; clk ; None ; None ; 2.447 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st2 ; cur_state.st0 ; clk ; clk ; None ; None ; 2.401 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st4 ; cur_state.st2 ; clk ; clk ; None ; None ; 2.401 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st4 ; cur_state.st5 ; clk ; clk ; None ; None ; 2.400 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st5 ; cur_state.st2 ; clk ; clk ; None ; None ; 2.182 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st5 ; cur_state.st5 ; clk ; clk ; None ; None ; 2.181 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st3 ; cur_state.st0 ; clk ; clk ; None ; None ; 2.179 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st0 ; cur_state.st5 ; clk ; clk ; None ; None ; 2.079 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st0 ; cur_state.st1 ; clk ; clk ; None ; None ; 1.747 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; cur_state.st2 ; cur_state.st4 ; clk ; clk ; None ; None ; 1.343 ns ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-----------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-----------+---------------+----------+
; N/A ; None ; 7.579 ns ; choice[1] ; cur_state.st4 ; clk ;
; N/A ; None ; 7.388 ns ; choice[0] ; cur_state.st4 ; clk ;
; N/A ; None ; 6.922 ns ; choice[1] ; cur_state.st3 ; clk ;
; N/A ; None ; 6.731 ns ; choice[0] ; cur_state.st3 ; clk ;
; N/A ; None ; 6.568 ns ; din[1] ; cur_state.st2 ; clk ;
; N/A ; None ; 6.420 ns ; din[1] ; cur_state.st3 ; clk ;
; N/A ; None ; 6.417 ns ; din[0] ; cur_state.st2 ; clk ;
; N/A ; None ; 6.391 ns ; choice[1] ; cur_state.st0 ; clk ;
; N/A ; None ; 6.320 ns ; din[0] ; cur_state.st3 ; clk ;
; N/A ; None ; 6.313 ns ; choice[1] ; cur_state.st1 ; clk ;
; N/A ; None ; 6.200 ns ; choice[0] ; cur_state.st0 ; clk ;
; N/A ; None ; 6.089 ns ; choice[0] ; cur_state.st1 ; clk ;
; N/A ; None ; 5.901 ns ; din[1] ; cur_state.st0 ; clk ;
; N/A ; None ; 5.884 ns ; din[1] ; cur_state.st1 ; clk ;
; N/A ; None ; 5.772 ns ; choice[1] ; cur_state.st5 ; clk ;
; N/A ; None ; 5.763 ns ; din[1] ; cur_state.st4 ; clk ;
; N/A ; None ; 5.734 ns ; din[0] ; cur_state.st1 ; clk ;
; N/A ; None ; 5.689 ns ; din[0] ; cur_state.st4 ; clk ;
; N/A ; None ; 5.670 ns ; choice[0] ; cur_state.st5 ; clk ;
; N/A ; None ; 5.489 ns ; din[0] ; cur_state.st0 ; clk ;
; N/A ; None ; 5.457 ns ; choice[1] ; cur_state.st2 ; clk ;
; N/A ; None ; 5.449 ns ; din[0] ; cur_state.st5 ; clk ;
; N/A ; None ; 5.355 ns ; choice[0] ; cur_state.st2 ; clk ;
; N/A ; None ; 5.335 ns ; din[1] ; cur_state.st5 ; clk ;
+-------+--------------+------------+-----------+---------------+----------+
+---------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------------+----------------+------------+
; N/A ; None ; 11.681 ns ; cur_state.st4 ; give_change[0] ; clk ;
; N/A ; None ; 11.397 ns ; cur_state.st4 ; give_change[1] ; clk ;
; N/A ; None ; 11.184 ns ; cur_state.st5 ; give_change[0] ; clk ;
; N/A ; None ; 11.075 ns ; cur_state.st4 ; commodity[1] ; clk ;
; N/A ; None ; 10.900 ns ; cur_state.st5 ; give_change[1] ; clk ;
; N/A ; None ; 10.642 ns ; cur_state.st4 ; commodity[0] ; clk ;
; N/A ; None ; 10.578 ns ; cur_state.st5 ; commodity[1] ; clk ;
; N/A ; None ; 10.145 ns ; cur_state.st5 ; commodity[0] ; clk ;
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