cpld4gdf00.map.summary

用maxplus2实现的一种通用逻辑模块

Flow Status : Successful - Wed Dec 28 19:27:05 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : cpld4gdf00
Top-level Entity Name : cpld4gdf00
Family : MAX7000S
Device : EPM7128SQC160-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 59
Total pins : 92