td_init asynchronous slave fifo data transfers.txt

本数据包提供用cy7c68013开发usb的完整源代码

TD_Init():             // TD_init asynchronously to in data transfer
{       
	REVCTL = 0x03;              // MUST set REVCTL.0 and REVCTL.1 to 1
	SYNCDELAY;
	FIFORESET = 0x80;            // reset all FIFOs
	SYNCDELAY;
	FIFORESET = 0x02;
	SYNCDELAY;
	FIFORESET = 0x04;
	SYNCDELAY;
	FIFORESET = 0x06;
	SYNCDELAY;
	FIFORESET = 0x08;
	SYNCDELAY;
	PORTACFG=0X00;  // SET PORTA0,PORTA1 TO OUTPUT I/O FOR HOST READ AND WRITE; 
	SYNCDELAY;
	OEA=0X00;
	SYNCDELAY;
	FIFORESET = 0x00;
        CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;   // CPUCLK=48MKHZ  0X08;BIT 3,4=1;
	SYNCDELAY;            // this defines the external interface to be the following:
	IFCONFIG = 0xcb;            // use internal IFCLK (48MHz)
                          // use slave FIFO interface pins asynchronously to external master
	EP6FIFOCFG = 0x0D;              // this lets the FX2 auto commit IN packets, gives 
                         // theability to send zero length packets,
                            // and sets the slave FIFO data interface to 16-bits
	EP6CFG = 0xE2;              // sets EP8 valid for IN's
                            // and defines the endpoint for 512 byte packets, 2x buffered
	PINFLAGSAB = 0x00;          // defines FLAGA as prog-level flag, pointed to by                                     //FIFOADR[1:0]
	SYNCDELAY;                 // FLAGB as full flag, as pointed to by FIFOADR[1:0]
	PINFLAGSCD = 0x00;            // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
                              // won't generally need FLAGD
	PORTACFG = 0x00;                // used PA7/FLAGD as a port pin, not as a FIFO flag
	FIFOPINPOLAR = 0x3F;              // @@set all slave FIFO interface pins as active                                           //HIGH
	SYNCDELAY;
	EP6AUTOINLENH = 0x02;            // you can define these as you wish,
	SYNCDELAY;                  // to have the FX2 automatically limit IN's
	EP6AUTOINLENL = 0x00;
	SYNCDELAY;
	EP6FIFOPFH = 0x81;              //  greater than/equal to (DECIS=1)(bit7) the 
                                 //   threshold.512byte
                             //you candefine the programmable flag (FLAGA)
	SYNCDELAY;                       // to be active at the level you wish
	EP6FIFOPFL = 0x00;
	SYNCDELAY;              // out endpoints do not POR (power-on reset) armed



    	// asynchronously auto_out slave init

    	EP2CFG = 0xA0; // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x
    	SYNCDELAY;
    	EP2FIFOCFG = 0x11; // EP2 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=1
    	SYNCDELAY;
    	OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump”
    	SYNCDELAY;
    	OUTPKTEND = 0x82;
}