sop_subm.v

来自「本人正在学习vhdl语言」· Verilog 代码 · 共 34 行

//
// Module : SOP_SUBM
//
// Description : Implementing SOP using MUXCY and ORCY
//
// Device : Virtex-II Family
//
//-----------------------------------------------------------------------------
`include "AND_LOGIC.v"
`include "AND_CHAIN.v"


module SOP_SUBM(and_in, sop_out);

input [63:0] and_in;
output sop_out;
wire out_andor_chain1, out_andor_chain2, out_andor_chain3;
wire GND = 1'b0;

AND_CHAIN u4(.data_in(and_in[63:48]), .carry_in(out_andor_chain3), 
               .out_andor_chain(sop_out));

AND_CHAIN u3(.data_in(and_in[47:32]), .carry_in(out_andor_chain2), 
               .out_andor_chain(out_andor_chain3));

AND_CHAIN u2(.data_in(and_in[31:16]), .carry_in(out_andor_chain1), 
              .out_andor_chain(out_andor_chain2));

AND_CHAIN u1(.data_in(and_in[15:0]), .carry_in(GND), 
               .out_andor_chain(out_andor_chain1));

endmodule