and_chain.v

本人正在学习vhdl语言

//
// Module : AND_CHAIN
//
// Description : 16 input AND gate 
//
// Device : Virtex-II Family
//
//---------------------------------------------------------------------------
module AND_CHAIN(data_in, carry_in, out_andor_chain);
input [15:0] data_in;
input carry_in;
output out_andor_chain;

wire VCC = 1'b1;
wire out_and_chain;
wire dat_out1, data_out2, data_out3;

AND_LOGIC u4(.sel_data(data_in[15:12]), .data_cin(data_out3), .data_out(out_and_chain));

AND_LOGIC u3(.sel_data(data_in[11:8]), .data_cin(data_out2), .data_out(data_out3));

AND_LOGIC u2(.sel_data(data_in[7:4]), .data_cin(data_out1), .data_out(data_out2));

AND_LOGIC u1(.sel_data(data_in[3:0]), .data_cin(VCC), .data_out(data_out1));

ORCY  u5(.I(out_and_chain), .CI(carry_in), .O(out_andor_chain));

endmodule