and_logic.v

本人正在学习vhdl语言

//
// Module AND_LOGIC
//
// Description : 4-input AND gate
//
// Device : Virtex-II Family
//
//-----------------------------------------------------------------------------------
//
module AND_LOGIC(sel_data, data_cin, data_out);

input[3:0] sel_data;
input data_cin;

output data_out;

wire GND = 1'b0;
wire VCC = 1'b1;
wire and_out;

assign and_out = sel_data[3] & sel_data[2] & sel_data[1] & sel_data[0];

MUXCY  muxcy_inst (.DI(GND), .CI(data_cin), .S(and_out), .O(data_out));

endmodule