srlc64e.v

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//
// Module: 	SRLC64E
//
// Description: Verilog instantiation template
//		SelectShiftRegister-II 
//		64 bit Shift Register with Carry and Clock Enable
//		Use Macro SRLC64E_MACRO.v
//
// Device: 	VIRTEX-II Family
//
// Date:	SAK / 04-17-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//-----------------------------------------------------------------------------------------------------


//64-bit SelectShiftRegister-II Macro Instantiation
   SRLC64E_MACRO U_SRLC64E_MACRO   ( .D(),          //insert Data_In signal
				     .A0(),         //insert first bit of the Address bus
				     .A1(),         //insert second bit of the Address bus
				     .A2(),         //insert third bit of the Address bus
				     .A3(),         //insert forth bit of the Address bus
				     .A4(),         //insert fifth bit of the Address bus
				     .A5(),         //insert sixth bit of the Address bus
                        	     .CLK(),        //insert Clock 
                         	     .CE(),         //insert Clock Enable
                        	     .Q(),          //insert Addressable Data_Out
                        	     .Q64()         //insert Last bit Data_Out
		     		   );