srl16e.v

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//
// Module: 	SRL16E
//
// Description: Verilog instantiation template
//		SelectShiftRegister-II 
//		16 bit Shift Register with Clock Enable
//		
//
// Device: 	VIRTEX-II Family
//
// Date:	SAK / 04-17-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//-----------------------------------------------------------------------------------------------------

// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

        //Shift Register initialization ("0" by default) for functional simulation:
	U_SRLC16E.INIT = 16'h0000;
// synopsys translate_on	


//SelectShiftRegister-II Instantiation
   SRLC16E U_SRLC16E   ( .D(),
			 .A0(),
                         .A1(),
                         .A2(),
                         .A3(),
                         .CLK(),
                         .CE(),
                         .Q()
		       );


// synthesis attribute declarations
  /* synopsys attribute 

	INIT "0000"
  */