srlc64e_macro.v

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//
// Module: 	SRLC64E
//
// Description: SelectShiftRegister-II macro
//		64 bit Shift Register with Carry and Clock Enable
//		Use template "SRLC16E.v"
//
// Device: 	VIRTEX-II Family
//
// Date:	SAK / 04-17-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//-----------------------------------------------------------------------------------------------------

module SRLC64E (D, CE, CLK, A0, A1, A2, A3, A4, A5, Q, Q64);

input D;
input CLK;
input CE;
input A0, A1, A2, A3, A4, A5;

output Q;
output Q64;

wire Q15;
wire Q31;
wire Q47;
wire Q_MUX_00_15;
wire Q_MUX_16_31;
wire Q_MUX_32_47;
wire Q_MUX_48_63;
wire F5_MUXOUT_00_31;
wire F5_MUXOUT_32_63;



//Instantiate 16-bit shift registers: SRLC16E//
   SRLC16E U_SRLC16E_0 ( .D(D),
			 .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_00_15),
                         .Q15(Q15)
		       );

   SRLC16E U_SRLC16E_1 ( .D(Q15),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_16_31),
                         .Q15(Q31) 
			);

   SRLC16E U_SRLC16E_2 ( .D(Q31),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_32_47),
                         .Q15(Q47) 
			);

   SRLC16E U_SRLC16E_3 ( .D(Q47),
                         .A0(A0),
                         .A1(A1),
                         .A2(A2),
                         .A3(A3),
                         .CLK(CLK),
                         .CE(CE),
                         .Q(Q_MUX_48_63),
                         .Q15(Q64) 
			);


//Instantiate MUXF5, and F6 for Addressable output//
    MUXF5_L  U0_MUX5_L ( .O(F5_MUXOUT_00_31),
                         .I0(Q_MUX_00_15),
                         .I1(Q_MUX_16_31),
                         .S(A4)
			);

    MUXF5_L  U1_MUX5_L ( .O(F5_MUXOUT_32_63),
                         .I0(Q_MUX_32_47),
                         .I1(Q_MUX_48_63),
                         .S(A4)
			);

    MUXF6      U_MUX6  ( .O(Q),
                         .I0(F5_MUXOUT_00_31),
                         .I1(F5_MUXOUT_32_63),
                         .S(A5)
			);



endmodule