unsigned_mult_17x17_rr.v

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//
// Module: UNSIGNED_MULT_17X17
//
// Description: Verilog Sub-module
// 17-bit X 17-bit embedded unsigned multiplier (asynchronous)

//
// Device: Virtex-II Family
//
// Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//
////////////////////////////////////////////////////////////////////////////////////
//

module UNSIGNED_MULT_17X17 (A, B, P, CLK, RESET);

input CLK;
input RESET;

input [16:0] A;
input [16:0] B;

output [33:0] P;
wire [33:0] P;

reg [16:0] ar, br;
reg [33:0] pr;
wire [33:0] p_async;

always @ (posedge CLK or posedge RESET)
if (RESET)
  begin
    ar <= 17'h0;
    br <= 17'h0;
    pr <= 34'h0;
  end
else
  begin
    ar <= A;
    br <= B;
    pr <= p_async;
  end

assign P = pr;


//
// Instantiation Section
//

MULT17X17_U DUT
  ( .A (ar) , // insert input signal #1
    .B (br) , // insert input signal #2
    .P (p_async)   // insert output signal
  );

//
////////////////////////////////////////////////////////////////////////////////////

endmodule