readme_multipliers_verilog.txt

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README file: Virtex-II Platform FPGA Handbook
=============================================

Date: March, 2001

Verilog code examples are provided to illustrate the Chapter 2 - Design Considerations - of 
the Virtex-II Platform FPFA Handbook.

- Verilog Templates:
Verilog templates are available as examples to instantiate primitives. 

- Verilog Submodules:
Verilog submodules are low level Verilog code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

The templates and submodules can be found in the following directories corresponding to 
each section of the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)

Directory:
------------

- multipliers: "Using Embedded Multipliers"

Templates (primitive):
 MULT18X18.v

Submodules (code example):
 mult17x17.v
 mult4x4_s.v
 mult4x4_u.v
 mult8x8_s.v
 mult8x8_u.v
 signed_mult18x18.v
 signed_mult_4x4_rr.v
 signed_mult_8x8_rr.v
 unsigned_mult_17x17_rr.v
 unsigned_mult_8x8_rr.v
 unsigned_mult_8x8_rr.v

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