mux_16_1.v

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//
// Module: 	MUX_16_1
// Design: 	TOP_ MUXES
//
// Description: Multiplexer 16:1
//
// Device: 	VIRTEX-II Family 
//
// Date:	SAK / 04-28-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR/
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//---------------------------------------------------------------------------------------
//
module MUX_16_1 (DATA_I, SELECT_I, DATA_O);

input [15:0]DATA_I;
input [3:0]SELECT_I;

output DATA_O;

wire [2:0]SELECT;

reg DATA_LSB;
reg DATA_MSB;


assign SELECT[2:0] = SELECT_I[2:0];

/*
//If synthesis tools supports MUXF7 :
always @ (DATA_I or SELECT_I)

    case (SELECT_I)
        4'b0000 : DATA_O <= DATA_I[0];
	4'b0001 : DATA_O <= DATA_I[1];
	4'b0010 : DATA_O <= DATA_I[2];
	4'b0011 : DATA_O <= DATA_I[3];
        4'b0100 : DATA_O <= DATA_I[4];
	4'b0101 : DATA_O <= DATA_I[5];
	4'b0110 : DATA_O <= DATA_I[6];
	4'b0111 : DATA_O <= DATA_I[7];
        4'b1000 : DATA_O <= DATA_I[8];
	4'b1001 : DATA_O <= DATA_I[9];
	4'b1010 : DATA_O <= DATA_I[10];
	4'b1011 : DATA_O <= DATA_I[11];
        4'b1100 : DATA_O <= DATA_I[12];
	4'b1101 : DATA_O <= DATA_I[13];
	4'b1110 : DATA_O <= DATA_I[14];
	4'b1111 : DATA_O <= DATA_I[15];
	default : DATA_O <= 1'bx;
    endcase
*/

always @ (SELECT or DATA_I)

    case (SELECT)
        3'b000 : DATA_LSB <= DATA_I[0];
	3'b001 : DATA_LSB <= DATA_I[1];
	3'b010 : DATA_LSB <= DATA_I[2];
	3'b011 : DATA_LSB <= DATA_I[3];
        3'b100 : DATA_LSB <= DATA_I[4];
	3'b101 : DATA_LSB <= DATA_I[5];
	3'b110 : DATA_LSB <= DATA_I[6];
	3'b111 : DATA_LSB <= DATA_I[7];
	default : DATA_LSB <= 1'bx;
    endcase


always @ (SELECT or DATA_I)

    case (SELECT)
        3'b000 : DATA_MSB <= DATA_I[8];
	3'b001 : DATA_MSB <= DATA_I[9];
	3'b010 : DATA_MSB <= DATA_I[10];
	3'b011 : DATA_MSB <= DATA_I[11];
        3'b100 : DATA_MSB <= DATA_I[12];
	3'b101 : DATA_MSB <= DATA_I[13];
	3'b110 : DATA_MSB <= DATA_I[14];
	3'b111 : DATA_MSB <= DATA_I[15];
	default : DATA_MSB <= 1'bx;
    endcase

// MUXF7 instantiation

MUXF7 U_MUXF7   (.I0(DATA_LSB),
		 .I1(DATA_MSB),
		 .S(SELECT_I[3]),
		 .O(DATA_O)
		);


endmodule