mux_32_1.v

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//
// Module: 	MUX_32_1
// Design: 	TOP_ MUXES
//
// Description: Multiplexer 32:1
//
// Device: 	VIRTEX-II Family 
//
// Date:	SAK / 04-28-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR/
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//---------------------------------------------------------------------------------------
//
module MUX_32_1 (DATA_I, SELECT_I, DATA_O);

input [31:0]DATA_I;
input [4:0]SELECT_I;

output DATA_O;

reg DATA_LSB_0;
reg DATA_LSB_1;
reg DATA_MSB_0;
reg DATA_MSB_1;

wire DATA_LSB;
wire DATA_MSB;

wire [2:0]SELECT;
assign SELECT[2:0] = SELECT_I[2:0];

/*
//If synthesis tools supports MUXF7 & MUXF8:
always @ (DATA_I or SELECT_I)

    case (SELECT_I)
        5'b00000 : DATA_O <= DATA_I[0];
	5'b00001 : DATA_O <= DATA_I[1];
	5'b00010 : DATA_O <= DATA_I[2];
	5'b00011 : DATA_O <= DATA_I[3];
        5'b00100 : DATA_O <= DATA_I[4];
	5'b00101 : DATA_O <= DATA_I[5];
	5'b00110 : DATA_O <= DATA_I[6];
	5'b00111 : DATA_O <= DATA_I[7];
        5'b01000 : DATA_O <= DATA_I[8];
	5'b01001 : DATA_O <= DATA_I[9];
	5'b01010 : DATA_O <= DATA_I[10];
	5'b01011 : DATA_O <= DATA_I[11];
        5'b01100 : DATA_O <= DATA_I[12];
	5'b01101 : DATA_O <= DATA_I[13];
	5'b01110 : DATA_O <= DATA_I[14];
	5'b01111 : DATA_O <= DATA_I[15];
	5'b10000 : DATA_O <= DATA_I[16];
	5'b10001 : DATA_O <= DATA_I[17];
	5'b10010 : DATA_O <= DATA_I[18];
	5'b10011 : DATA_O <= DATA_I[19];
        5'b10100 : DATA_O <= DATA_I[20];
	5'b10101 : DATA_O <= DATA_I[21];
	5'b10110 : DATA_O <= DATA_I[22];
	5'b10111 : DATA_O <= DATA_I[23];
        5'b11000 : DATA_O <= DATA_I[24];
	5'b11001 : DATA_O <= DATA_I[25];
	5'b11010 : DATA_O <= DATA_I[26];
	5'b11011 : DATA_O <= DATA_I[27];
        5'b11100 : DATA_O <= DATA_I[28];
	5'b11101 : DATA_O <= DATA_I[29];
	5'b11110 : DATA_O <= DATA_I[30];
	5'b11111 : DATA_O <= DATA_I[31];
	default : DATA_O <= 1'bx;
    endcase
*/


always @ (SELECT or DATA_I)

    case (SELECT)
        3'b000 : DATA_LSB_0 <= DATA_I[0];
	3'b001 : DATA_LSB_0 <= DATA_I[1];
	3'b010 : DATA_LSB_0 <= DATA_I[2];
	3'b011 : DATA_LSB_0 <= DATA_I[3];
        3'b100 : DATA_LSB_0 <= DATA_I[4];
	3'b101 : DATA_LSB_0 <= DATA_I[5];
	3'b110 : DATA_LSB_0 <= DATA_I[6];
	3'b111 : DATA_LSB_0 <= DATA_I[7];
	default : DATA_LSB_0 <= 1'bx;
    endcase

always @ (SELECT or DATA_I)

    case (SELECT)
        3'b000 : DATA_LSB_1 <= DATA_I[8];
	3'b001 : DATA_LSB_1 <= DATA_I[9];
	3'b010 : DATA_LSB_1 <= DATA_I[10];
	3'b011 : DATA_LSB_1 <= DATA_I[11];
        3'b100 : DATA_LSB_1 <= DATA_I[12];
	3'b101 : DATA_LSB_1 <= DATA_I[13];
	3'b110 : DATA_LSB_1 <= DATA_I[14];
	3'b111 : DATA_LSB_1 <= DATA_I[15];
	default : DATA_LSB_1 <= 1'bx;
    endcase

always @ (SELECT or DATA_I)

    case (SELECT)
        3'b000 : DATA_MSB_0 <= DATA_I[16];
	3'b001 : DATA_MSB_0 <= DATA_I[17];
	3'b010 : DATA_MSB_0 <= DATA_I[18];
	3'b011 : DATA_MSB_0 <= DATA_I[19];
        3'b100 : DATA_MSB_0 <= DATA_I[20];
	3'b101 : DATA_MSB_0 <= DATA_I[21];
	3'b110 : DATA_MSB_0 <= DATA_I[22];
	3'b111 : DATA_MSB_0 <= DATA_I[23];
	default : DATA_MSB_0 <= 1'bx;
    endcase

always @ (SELECT or DATA_I)

    case (SELECT)
        3'b000 : DATA_MSB_1 <= DATA_I[24];
	3'b001 : DATA_MSB_1 <= DATA_I[25];
	3'b010 : DATA_MSB_1 <= DATA_I[26];
	3'b011 : DATA_MSB_1 <= DATA_I[27];
        3'b100 : DATA_MSB_1 <= DATA_I[28];
	3'b101 : DATA_MSB_1 <= DATA_I[29];
	3'b110 : DATA_MSB_1 <= DATA_I[30];
	3'b111 : DATA_MSB_1 <= DATA_I[31];
	default : DATA_MSB_1 <= 1'bx;
    endcase

// MUXF7 instantiation LSB

MUXF7 U0_MUXF7  (.I0(DATA_LSB_0),
		 .I1(DATA_LSB_1),
		 .S(SELECT_I[3]),
		 .O(DATA_LSB)
		);

// MUXF7 instantiation MSB

MUXF7 U1_MUXF7  (.I0(DATA_MSB_0),
		 .I1(DATA_MSB_1),
		 .S(SELECT_I[3]),
		 .O(DATA_MSB)
		);

// MUFF8 instantiation

MUXF8 U_MUXF8   (.I0(DATA_LSB),
		 .I1(DATA_MSB),
		 .S(SELECT_I[4]),
		 .O(DATA_O)
		);
endmodule