mux_8_1.v

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//
// Module: 	MUX_8_1
// Design: 	TOP_ MUXES
//
// Description: Multiplexer 8:1
//
// Device: 	VIRTEX-II Family 
//
// Date:	SAK / 04-28-2000 - XILINX
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR/
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 2000 Xilinx, Inc.  All rights reserved.
//---------------------------------------------------------------------------------------
//
module MUX_8_1 (DATA_I, SELECT_I, DATA_O);

input [7:0]DATA_I;
input [2:0]SELECT_I;

output DATA_O;
reg DATA_O;


always @ (DATA_I or SELECT_I)

    case (SELECT_I)
        3'b000 : DATA_O <= DATA_I[0];
	3'b001 : DATA_O <= DATA_I[1];
	3'b010 : DATA_O <= DATA_I[2];
	3'b011 : DATA_O <= DATA_I[3];
        3'b100 : DATA_O <= DATA_I[4];
	3'b101 : DATA_O <= DATA_I[5];
	3'b110 : DATA_O <= DATA_I[6];
	3'b111 : DATA_O <= DATA_I[7];
	default : DATA_O <= 1'bx;
    endcase

endmodule