ddr_lvds_in.v

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//
// Module:      DDR_LVDS_IN 
//
// Description: Verilog Instantiation Template
//		DDR Input Flip-Flops with LVDS input buffer
//		
//
// Device: 	VIRTEX-II Family 
//
//---------------------------------------------------------------------
//
//DDR Input Flip-Flops
//

always @ (posedge clk or posedge rst)

  begin
	if (rst) 
	   q1 = 1'b0;
	else 
	   q1 = data_in; // data_in = Output from LVDS input buffer
  end 

always @ (negedge clk or posedge rst)

begin
	if (rst) 
	   q2 = 1'b0;
	else 
	   q2 = data_in; // data_in = Output from LVDS input buffer
  end 

/* NOTE: You must include the following constraints in the .ucf file when running back-end tools, \
	in order to ensure that IOB DDR registers are used:

INST "q2_reg" IOB=TRUE;
INST "q1_reg" IOB=TRUE;

Depending on the synthesis tools you use, it may be required to check the edif file for modifications to 
original net names...in this case, Synopsis changed the names: q1 and q2 to q1_reg and q2_reg

*/

//3-State LVDS buffer instantiation

IBUFDS_LVDS_25 U1 ( .I(), // P-Channel input to LVDS input buffer
		    .IB(),// N-Channel input to LVDS input buffer
		    .O()  // Output from LVDS input buffer
		  );

//---------------------------------------------------------------------