bufg_clk2x_subm.v

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//
// Module:      BUFG_CLK2X_SUBM
//
// Description: Verilog Submodule
//		DCM with CLK2X deskew
//		
// Device: 	VIRTEX-II Family 
//
//---------------------------------------------------------------------

module BUFG_CLK2X_SUBM ( 
                        CLK_IN,
                        RST,
                        CLK2X,
                        LOCK
                        );
    input CLK_IN;
    input RST;

    output CLK2X;
    output LOCK;

    wire CLK2X_W;
    wire GND;

    assign GND = 1'b0;

    // BUFG Instantiation//
    BUFG U_BUFG (
                 .I(CLK2X_W), 
                 .O(CLK2X)
                 );
 	 
    // Attributes for functional simulation//
    // synopsys translate_off
    defparam U_DCM.DLL_FREQUENCY_MODE = "LOW";
    defparam U_DCM.DUTY_CYCLE_CORRECTION = "TRUE";
    defparam U_DCM.STARTUP_WAIT = "FALSE";
    // synopsys translate_on

    // Instantiate the DCM primitive//
    DCM U_DCM ( 
               .CLKFB(CLK2X), 
               .CLKIN(CLK_IN), 
               .DSSEN(GND), 
               .PSCLK(GND), 
               .PSEN(GND), 
               .PSINCDEC(GND), 
               .RST(RST), 
               .CLK2X(CLK2X_W), 
               .LOCKED(LOCK)
               );
    
   // synthesis attribute declarations
   /* synopsys attribute
 
   DLL_FREQUENCY_MODE "LOW"
   DUTY_CYCLE_CORRECTION "TRUE"
   STARTUP_WAIT "FALSE"
   */	 
endmodule