selectram_a4_b18.v

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//
// Module: 	SelectRAM_A4_B18
//
// Description: Verilog instantiation template
//		Block SelectRAM
//		Dual Port A:4096 x 4 bits & B:1024 x 18 bits
//
// Device: 	VIRTEX-II Family 
//-------------------------------------------------------------------------------------------
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

//"Read during Write" attribute for functional simulation
	U_RAMB16_S4_S18.WRITE_MODE_A = "READ_FIRST" -type string; //WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE 
	U_RAMB16_S4_S18.WRITE_MODE_B = "WRITE_FIRST" -type string; //WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE 
//RAM initialization ("0" by default) for functional simulation: see example

// synopsys translate_on	


//Block SelectRAM Instantiation
RAMB16_S4_S18 U_RAMB16_S4_S18  (  .DIA(),    //insert 4-bit data_in bus ([3:0]) 
			          .ADDRA(),  //insert 12-bit address bus ([11:0])
			          .ENA(),    //insert enable signal
		 	          .WEA(),    //insert write enable signal
			          .SSRA(),   //insert set/reset signal
			          .CLKA(),   //insert clock signal
			          .DOA(),    //insert 4-bit data_out bus ([3:0]) 
//
			          .DIB(),    //insert 16-bit data_in bus ([15:0]) 
				  .DIPB(),   //insert 2-bit parity data_in bus ([17:16])
			          .ADDRB(),  //insert 10-bit address bus ([9:0])
			          .ENB(),    //insert enable signal
		 	          .WEB(),    //insert write enable signal
			          .SSRB(),   //insert set/reset signal
			          .CLKB(),   //insert clock signal
			          .DOB(),    //insert 16-bit data_out bus ([15:0]) 
				  .DOPB()    //insert 2-bit parity data_out bus ([17:16])
				   );
			    

// Attribute Decalrations:
  /* synopsys attribute 

Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE

	WRITE_MODE_A "READ_FIRST"
	WRTIE_MODE_B "WRITE_FIRST"
	*/
//Attributes for RAM initialization ("0" by default): see example