selectram_a36.v

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//
// Module: 	SelectRAM_A36
//
// Description: Verilog instantiation template
//		Block SelectRAM
//		Single Port 512 x 36 bits
//
// Device: 	VIRTEX-II Family 
//-------------------------------------------------------------------------------------------
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

//"Read during Write" attribute for functional simulation
	U_RAMB16_S36.WRITE_MODE = "READ_FIRST" -type string; //WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE 
//RAM initialization ("0" by default) for functional simulation: see example

// synopsys translate_on	


//Block SelectRAM Instantiation
RAMB16_S36 U_RAMB16_S36 (   .DI(),    //insert 32-bit data_in bus ([31:0])
			    .DIP(),   //insert 4-bit parity data_in bus ([35:32])
 			    .ADDR(),  //insert 9-bit address bus ([8:0])
			    .EN(),    //insert enable signal
		 	    .WE(),    //insert write enable signal
			    .SSR(),   //insert set/reset signal
			    .CLK(),   //insert clock signal
			    .DO(),    //insert 32-bit data_out bus ([31:0])
			    .DOP()    //insert 4-bit parity data_out bus ([35:32])
			     );

// Attribute Decalrations:
  /* synopsys attribute 

Attribute "Read during Write mode" = WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE

	WRITE_MODE "READ_FIRST"
	*/
//Attributes for RAM initialization ("0" by default): see example