mcode.tan.qmsg

一个典型的m序列发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register m\[2\] m\[2\] 390.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 390.02 MHz between source register \"m\[2\]\" and destination register \"m\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.564 ns " "Info: fmax restricted to clock pin edge rate 2.564 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.183 ns + Longest register register " "Info: + Longest register to register delay is 1.183 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m\[2\] 1 REG LC_X1_Y45_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "" { m[2] } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.513 ns) + CELL(0.670 ns) 1.183 ns m\[2\] 2 REG LC_X1_Y45_N2 2 " "Info: 2: + IC(0.513 ns) + CELL(0.670 ns) = 1.183 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "1.183 ns" { m[2] m[2] } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.670 ns 56.64 % " "Info: Total cell delay = 0.670 ns ( 56.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.513 ns 43.36 % " "Info: Total interconnect delay = 0.513 ns ( 43.36 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "1.183 ns" { m[2] m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.183 ns" { m[2] m[2] } { 0.000ns 0.513ns } { 0.000ns 0.670ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.717 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.717 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 3; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "" { clk } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.198 ns) + CELL(0.644 ns) 3.717 ns m\[2\] 2 REG LC_X1_Y45_N2 2 " "Info: 2: + IC(2.198 ns) + CELL(0.644 ns) = 3.717 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "2.842 ns" { clk m[2] } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 40.87 % " "Info: Total cell delay = 1.519 ns ( 40.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.198 ns 59.13 % " "Info: Total interconnect delay = 2.198 ns ( 59.13 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[2] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.717 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.717 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 3; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "" { clk } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.198 ns) + CELL(0.644 ns) 3.717 ns m\[2\] 2 REG LC_X1_Y45_N2 2 " "Info: 2: + IC(2.198 ns) + CELL(0.644 ns) = 3.717 ns; Loc. = LC_X1_Y45_N2; Fanout = 2; REG Node = 'm\[2\]'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "2.842 ns" { clk m[2] } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 40.87 % " "Info: Total cell delay = 1.519 ns ( 40.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.198 ns 59.13 % " "Info: Total interconnect delay = 2.198 ns ( 59.13 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[2] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[2] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[2] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "1.183 ns" { m[2] m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.183 ns" { m[2] m[2] } { 0.000ns 0.513ns } { 0.000ns 0.670ns } } } { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[2] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[2] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } }  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "" { m[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { m[2] } {  } {  } } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk code m\[0\] 7.445 ns register " "Info: tco from clock \"clk\" to destination pin \"code\" through register \"m\[0\]\" is 7.445 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.717 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.717 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.875 ns) 0.875 ns clk 1 CLK PIN_M24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.875 ns) = 0.875 ns; Loc. = PIN_M24; Fanout = 3; CLK Node = 'clk'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "" { clk } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.198 ns) + CELL(0.644 ns) 3.717 ns m\[0\] 2 REG LC_X1_Y45_N4 2 " "Info: 2: + IC(2.198 ns) + CELL(0.644 ns) = 3.717 ns; Loc. = LC_X1_Y45_N4; Fanout = 2; REG Node = 'm\[0\]'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "2.842 ns" { clk m[0] } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.519 ns 40.87 % " "Info: Total cell delay = 1.519 ns ( 40.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.198 ns 59.13 % " "Info: Total interconnect delay = 2.198 ns ( 59.13 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[0] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns + " "Info: + Micro clock to output delay of source is 0.202 ns" {  } { { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.526 ns + Longest register pin " "Info: + Longest register to pin delay is 3.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m\[0\] 1 REG LC_X1_Y45_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y45_N4; Fanout = 2; REG Node = 'm\[0\]'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "" { m[0] } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(2.495 ns) 3.526 ns code 2 PIN PIN_F4 0 " "Info: 2: + IC(1.031 ns) + CELL(2.495 ns) = 3.526 ns; Loc. = PIN_F4; Fanout = 0; PIN Node = 'code'" {  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.526 ns" { m[0] code } "NODE_NAME" } "" } } { "mcode.vhd" "" { Text "C:/altera/project/experiment/mcode/mcode.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.495 ns 70.76 % " "Info: Total cell delay = 2.495 ns ( 70.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns 29.24 % " "Info: Total interconnect delay = 1.031 ns ( 29.24 % )" {  } {  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.526 ns" { m[0] code } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.526 ns" { m[0] code } { 0.000ns 1.031ns } { 0.000ns 2.495ns } } }  } 0}  } { { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.717 ns" { clk m[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.717 ns" { clk clk~out0 m[0] } { 0.000ns 0.000ns 2.198ns } { 0.000ns 0.875ns 0.644ns } } } { "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" "" { Report "C:/altera/project/experiment/mcode/db/mcode_cmp.qrpt" Compiler "mcode" "UNKNOWN" "V1" "C:/altera/project/experiment/mcode/db/mcode.quartus_db" { Floorplan "C:/altera/project/experiment/mcode/" "" "3.526 ns" { m[0] code } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.526 ns" { m[0] code } { 0.000ns 1.031ns } { 0.000ns 2.495ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 15 10:07:53 2005 " "Info: Processing ended: Thu Dec 15 10:07:53 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}