cpu_mm_manager3.hier_info

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

|cpu_mm_manager3
reset => control_process_2~2.IN0
reset => MM_RE_0[1].PRESET
reset => MM_RE_0[2].PRESET
reset => MM_RE_0[3].ACLR
reset => MM_RE_0[4].PRESET
reset => MM_RE_0[5].PRESET
reset => MM_RE_0[6].ACLR
reset => MM_RE_0[7].ACLR
reset => MM_RE_1[0].PRESET
reset => MM_RE_1[1].PRESET
reset => MM_RE_1[2].ACLR
reset => MM_RE_1[3].PRESET
reset => MM_RE_1[4].PRESET
reset => MM_RE_1[5].PRESET
reset => MM_RE_1[6].ACLR
reset => MM_RE_1[7].ACLR
reset => MM_RE_2[0].PRESET
reset => MM_RE_2[1].ACLR
reset => MM_RE_2[2].PRESET
reset => MM_RE_2[3].PRESET
reset => MM_RE_2[4].ACLR
reset => MM_RE_2[5].PRESET
reset => MM_RE_2[6].ACLR
reset => MM_RE_2[7].PRESET
reset => MM_RE_3[0].ACLR
reset => MM_RE_3[1].ACLR
reset => MM_RE_3[2].ACLR
reset => MM_RE_3[3].ACLR
reset => MM_RE_3[4].ACLR
reset => MM_RE_3[5].ACLR
reset => MM_RE_3[6].ACLR
reset => MM_RE_3[7].ACLR
reset => MM_RE_4[0].ACLR
reset => MM_RE_4[1].ACLR
reset => MM_RE_4[2].ACLR
reset => MM_RE_4[3].ACLR
reset => MM_RE_4[4].ACLR
reset => MM_RE_4[5].ACLR
reset => MM_RE_4[6].ACLR
reset => MM_RE_4[7].ACLR
reset => MM_RE_5[0].PRESET
reset => MM_RE_5[1].ACLR
reset => MM_RE_5[2].PRESET
reset => MM_RE_5[3].ACLR
reset => MM_RE_5[4].ACLR
reset => MM_RE_5[5].ACLR
reset => MM_RE_5[6].ACLR
reset => MM_RE_5[7].PRESET
reset => MM_RE_6[0].ACLR
reset => MM_RE_6[1].ACLR
reset => MM_RE_6[2].PRESET
reset => MM_RE_6[3].PRESET
reset => MM_RE_6[4].ACLR
reset => MM_RE_6[5].ACLR
reset => MM_RE_6[6].ACLR
reset => MM_RE_6[7].PRESET
reset => MM_RE_7[0].ACLR
reset => MM_RE_7[1].PRESET
reset => MM_RE_7[2].ACLR
reset => MM_RE_7[3].PRESET
reset => MM_RE_7[4].ACLR
reset => MM_RE_7[5].ACLR
reset => MM_RE_7[6].ACLR
reset => MM_RE_7[7].PRESET
reset => MM_RE_8[0].PRESET
reset => MM_RE_8[1].ACLR
reset => MM_RE_8[2].ACLR
reset => MM_RE_8[3].PRESET
reset => MM_RE_8[4].ACLR
reset => MM_RE_8[5].PRESET
reset => MM_RE_8[6].ACLR
reset => MM_RE_8[7].ACLR
reset => MM_RE_9[0].ACLR
reset => MM_RE_9[1].ACLR
reset => MM_RE_9[2].PRESET
reset => MM_RE_9[3].ACLR
reset => MM_RE_9[4].ACLR
reset => MM_RE_9[5].ACLR
reset => MM_RE_9[6].ACLR
reset => MM_RE_9[7].PRESET
reset => MM_RE_A[0].ACLR
reset => MM_RE_A[1].ACLR
reset => MM_RE_A[2].ACLR
reset => MM_RE_A[3].ACLR
reset => MM_RE_A[4].ACLR
reset => MM_RE_A[5].ACLR
reset => MM_RE_A[6].ACLR
reset => MM_RE_A[7].ACLR
reset => MM_RE_B[0].ACLR
reset => MM_RE_B[1].ACLR
reset => MM_RE_B[2].ACLR
reset => MM_RE_B[3].ACLR
reset => MM_RE_B[4].ACLR
reset => MM_RE_B[5].ACLR
reset => MM_RE_B[6].ACLR
reset => MM_RE_B[7].ACLR
reset => MM_RE_C[0].ACLR
reset => MM_RE_C[1].ACLR
reset => MM_RE_C[2].ACLR
reset => MM_RE_C[3].ACLR
reset => MM_RE_C[4].ACLR
reset => MM_RE_C[5].ACLR
reset => MM_RE_C[6].ACLR
reset => MM_RE_C[7].ACLR
reset => MM_RE_D[0].ACLR
reset => MM_RE_D[1].ACLR
reset => MM_RE_D[2].ACLR
reset => MM_RE_D[3].ACLR
reset => MM_RE_D[4].ACLR
reset => MM_RE_D[5].ACLR
reset => MM_RE_D[6].ACLR
reset => MM_RE_D[7].ACLR
reset => MM_RE_E[0].ACLR
reset => MM_RE_E[1].ACLR
reset => MM_RE_E[2].ACLR
reset => MM_RE_E[3].ACLR
reset => MM_RE_E[4].ACLR
reset => MM_RE_E[5].ACLR
reset => MM_RE_E[6].ACLR
reset => MM_RE_E[7].ACLR
reset => MM_RE_F[0].ACLR
reset => MM_RE_F[1].ACLR
reset => MM_RE_F[2].ACLR
reset => MM_RE_F[3].ACLR
reset => MM_RE_F[4].ACLR
reset => MM_RE_F[5].ACLR
reset => MM_RE_F[6].ACLR
reset => MM_RE_F[7].ACLR
reset => R0[1].PRESET
reset => MM_RE_0[0].PRESET
reset => R0[2].PRESET
reset => R0[3].ACLR
reset => R0[4].ACLR
reset => R0[5].PRESET
reset => R0[6].ACLR
reset => R0[7].PRESET
reset => R1[0].ACLR
reset => R1[1].ACLR
reset => R1[2].ACLR
reset => R1[3].ACLR
reset => R1[4].PRESET
reset => R1[5].ACLR
reset => R1[6].PRESET
reset => R1[7].PRESET
reset => R2[0].ACLR
reset => R2[1].ACLR
reset => R2[2].ACLR
reset => R2[3].ACLR
reset => R2[4].ACLR
reset => R2[5].PRESET
reset => R2[6].PRESET
reset => R2[7].PRESET
reset => A[1].ACLR
reset => R0[0].ACLR
reset => A[2].ACLR
reset => A[3].ACLR
reset => A[4].ACLR
reset => A[5].ACLR
reset => A[6].ACLR
reset => A[7].ACLR
reset => A[0].ACLR
reset => IR[1].ACLR
reset => IR[2].ACLR
reset => IR[3].ACLR
reset => IR[4].ACLR
reset => IR[5].ACLR
reset => IR[6].ACLR
reset => IR[7].ACLR
reset => IR[0].ACLR
reset => IR_in.ACLR
reset => A_in.ACLR
reset => R_Enable.ACLR
reset => R_in[0].PRESET
reset => R_in[1].PRESET
reset => DataorALU_to_bus.PRESET
reset => R_to_ALU[0].PRESET
reset => R_to_ALU[1].PRESET
reset => control_process_2~3.PRESET
reset => IP_out[1].ACLR
reset => IP_out[2].ACLR
reset => IP_out[3].ACLR
reset => IP_out[0].ACLR
reset => R_out[0].ENA
reset => R_out[1].ENA
reset => R_out[2].ENA
reset => R_out[3].ENA
reset => R_out[4].ENA
reset => R_out[5].ENA
reset => R_out[6].ENA
reset => R_out[7].ENA
reset => ReadMEM.ENA
reset => WriteMEM.ENA
reset => IP_in[0].ENA
reset => IP_in[1].ENA
reset => DataOut_to_bus.ENA
reset => statement~5.IN1
clk => R0[1].CLK
clk => R0[2].CLK
clk => R0[3].CLK
clk => R0[4].CLK
clk => R0[5].CLK
clk => R0[6].CLK
clk => R0[7].CLK
clk => R1[0].CLK
clk => R1[1].CLK
clk => R1[2].CLK
clk => R1[3].CLK
clk => R1[4].CLK
clk => R1[5].CLK
clk => R1[6].CLK
clk => R1[7].CLK
clk => R2[0].CLK
clk => R2[1].CLK
clk => R2[2].CLK
clk => R2[3].CLK
clk => R2[4].CLK
clk => R2[5].CLK
clk => R2[6].CLK
clk => R2[7].CLK
clk => R_out[0].CLK
clk => R_out[1].CLK
clk => R_out[2].CLK
clk => R_out[3].CLK
clk => R_out[4].CLK
clk => R_out[5].CLK
clk => R_out[6].CLK
clk => R_out[7].CLK
clk => A[0].CLK
clk => A[1].CLK
clk => A[2].CLK
clk => A[3].CLK
clk => A[4].CLK
clk => A[5].CLK
clk => A[6].CLK
clk => A[7].CLK
clk => IR[0].CLK
clk => IR[1].CLK
clk => IR[2].CLK
clk => IR[3].CLK
clk => IR[4].CLK
clk => IR[5].CLK
clk => IR[6].CLK
clk => IR[7].CLK
clk => IR_in.CLK
clk => A_in.CLK
clk => R_Enable.CLK
clk => R_in[0].CLK
clk => R_in[1].CLK
clk => DataorALU_to_bus.CLK
clk => R_to_ALU[0].CLK
clk => R_to_ALU[1].CLK
clk => IPorAddrOut.CLK
clk => ReadMEM.CLK
clk => WriteMEM.CLK
clk => IP_in[0].CLK
clk => IP_in[1].CLK
clk => DataOut_to_bus.CLK
clk => control_process_2~3.CLK
clk => control_process_2~0.CLK
clk => IP_out[0].CLK
clk => IP_out[1].CLK
clk => IP_out[2].CLK
clk => IP_out[3].CLK
clk => MM_RE_0[0].CLK
clk => MM_RE_0[1].CLK
clk => MM_RE_0[2].CLK
clk => MM_RE_0[3].CLK
clk => MM_RE_0[4].CLK
clk => MM_RE_0[5].CLK
clk => MM_RE_0[6].CLK
clk => MM_RE_0[7].CLK
clk => MM_RE_1[0].CLK
clk => MM_RE_1[1].CLK
clk => MM_RE_1[2].CLK
clk => MM_RE_1[3].CLK
clk => MM_RE_1[4].CLK
clk => MM_RE_1[5].CLK
clk => MM_RE_1[6].CLK
clk => MM_RE_1[7].CLK
clk => MM_RE_2[0].CLK
clk => MM_RE_2[1].CLK
clk => MM_RE_2[2].CLK
clk => MM_RE_2[3].CLK
clk => MM_RE_2[4].CLK
clk => MM_RE_2[5].CLK
clk => MM_RE_2[6].CLK
clk => MM_RE_2[7].CLK
clk => MM_RE_3[0].CLK
clk => MM_RE_3[1].CLK
clk => MM_RE_3[2].CLK
clk => MM_RE_3[3].CLK
clk => MM_RE_3[4].CLK
clk => MM_RE_3[5].CLK
clk => MM_RE_3[6].CLK
clk => MM_RE_3[7].CLK
clk => MM_RE_4[0].CLK
clk => MM_RE_4[1].CLK
clk => MM_RE_4[2].CLK
clk => MM_RE_4[3].CLK
clk => MM_RE_4[4].CLK
clk => MM_RE_4[5].CLK
clk => MM_RE_4[6].CLK
clk => MM_RE_4[7].CLK
clk => MM_RE_5[0].CLK
clk => MM_RE_5[1].CLK
clk => MM_RE_5[2].CLK
clk => MM_RE_5[3].CLK
clk => MM_RE_5[4].CLK
clk => MM_RE_5[5].CLK
clk => MM_RE_5[6].CLK
clk => MM_RE_5[7].CLK
clk => MM_RE_6[0].CLK
clk => MM_RE_6[1].CLK
clk => MM_RE_6[2].CLK
clk => MM_RE_6[3].CLK
clk => MM_RE_6[4].CLK
clk => MM_RE_6[5].CLK
clk => MM_RE_6[6].CLK
clk => MM_RE_6[7].CLK
clk => MM_RE_7[0].CLK
clk => MM_RE_7[1].CLK
clk => MM_RE_7[2].CLK
clk => MM_RE_7[3].CLK
clk => MM_RE_7[4].CLK
clk => MM_RE_7[5].CLK
clk => MM_RE_7[6].CLK
clk => MM_RE_7[7].CLK
clk => MM_RE_8[0].CLK
clk => MM_RE_8[1].CLK
clk => MM_RE_8[2].CLK
clk => MM_RE_8[3].CLK
clk => MM_RE_8[4].CLK
clk => MM_RE_8[5].CLK
clk => MM_RE_8[6].CLK
clk => MM_RE_8[7].CLK
clk => MM_RE_9[0].CLK
clk => MM_RE_9[1].CLK
clk => MM_RE_9[2].CLK
clk => MM_RE_9[3].CLK
clk => MM_RE_9[4].CLK
clk => MM_RE_9[5].CLK
clk => MM_RE_9[6].CLK
clk => MM_RE_9[7].CLK
clk => MM_RE_A[0].CLK
clk => MM_RE_A[1].CLK
clk => MM_RE_A[2].CLK
clk => MM_RE_A[3].CLK
clk => MM_RE_A[4].CLK
clk => MM_RE_A[5].CLK
clk => MM_RE_A[6].CLK
clk => MM_RE_A[7].CLK
clk => MM_RE_B[0].CLK
clk => MM_RE_B[1].CLK
clk => MM_RE_B[2].CLK
clk => MM_RE_B[3].CLK
clk => MM_RE_B[4].CLK
clk => MM_RE_B[5].CLK
clk => MM_RE_B[6].CLK
clk => MM_RE_B[7].CLK
clk => MM_RE_C[0].CLK
clk => MM_RE_C[1].CLK
clk => MM_RE_C[2].CLK
clk => MM_RE_C[3].CLK
clk => MM_RE_C[4].CLK
clk => MM_RE_C[5].CLK
clk => MM_RE_C[6].CLK
clk => MM_RE_C[7].CLK
clk => MM_RE_D[0].CLK
clk => MM_RE_D[1].CLK
clk => MM_RE_D[2].CLK
clk => MM_RE_D[3].CLK
clk => MM_RE_D[4].CLK
clk => MM_RE_D[5].CLK
clk => MM_RE_D[6].CLK
clk => MM_RE_D[7].CLK
clk => MM_RE_E[0].CLK
clk => MM_RE_E[1].CLK
clk => MM_RE_E[2].CLK
clk => MM_RE_E[3].CLK
clk => MM_RE_E[4].CLK
clk => MM_RE_E[5].CLK
clk => MM_RE_E[6].CLK
clk => MM_RE_E[7].CLK
clk => MM_RE_F[0].CLK
clk => MM_RE_F[1].CLK
clk => MM_RE_F[2].CLK
clk => MM_RE_F[3].CLK
clk => MM_RE_F[4].CLK
clk => MM_RE_F[5].CLK
clk => MM_RE_F[6].CLK
clk => MM_RE_F[7].CLK
clk => Mem_DataOut[0].CLK
clk => Mem_DataOut[1].CLK
clk => Mem_DataOut[2].CLK
clk => Mem_DataOut[3].CLK
clk => Mem_DataOut[4].CLK
clk => Mem_DataOut[5].CLK
clk => Mem_DataOut[6].CLK
clk => Mem_DataOut[7].CLK
clk => AddrR_out[0].CLK
clk => AddrR_out[1].CLK
clk => AddrR_out[2].CLK
clk => AddrR_out[3].CLK
clk => R0[0].CLK
clk => statement~4.IN1
Initial => MM_Process~0.IN1
Initial => Select3_process~0.OUTPUTSELECT
Initial => Select3_process~2.OUTPUTSELECT
Initial => Select3_process~4.OUTPUTSELECT
Initial => Select3_process~6.OUTPUTSELECT
Initial => Select3_process~8.OUTPUTSELECT
Initial => Select3_process~10.OUTPUTSELECT
Initial => Select3_process~12.OUTPUTSELECT
Initial => Select3_process~14.OUTPUTSELECT
Initial => Select5_process~0.OUTPUTSELECT
Initial => Select5_process~2.OUTPUTSELECT
Initial => Select5_process~4.OUTPUTSELECT
Initial => Select5_process~6.OUTPUTSELECT
InitialData[7] => Select3_process~14.DATAB
InitialData[6] => Select3_process~12.DATAB
InitialData[5] => Select3_process~10.DATAB
InitialData[4] => Select3_process~8.DATAB
InitialData[3] => Select3_process~6.DATAB
InitialData[2] => Select3_process~4.DATAB
InitialData[1] => Select3_process~2.DATAB
InitialData[0] => Select3_process~0.DATAB
InitialAddr[3] => Select5_process~6.DATAB
InitialAddr[2] => Select5_process~4.DATAB
InitialAddr[1] => Select5_process~2.DATAB
InitialAddr[0] => Select5_process~0.DATAB
DataIn_out[7] <= Select4_process~15.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[6] <= Select4_process~13.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[5] <= Select4_process~11.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[4] <= Select4_process~9.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[3] <= Select4_process~7.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[2] <= Select4_process~5.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[1] <= Select4_process~3.DB_MAX_OUTPUT_PORT_TYPE
DataIn_out[0] <= Select4_process~1.DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[7] <= R0[7].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[6] <= R0[6].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[5] <= R0[5].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[4] <= R0[4].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[3] <= R0[3].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[2] <= R0[2].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[1] <= R0[1].DB_MAX_OUTPUT_PORT_TYPE
R0_OUT[0] <= R0[0].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[7] <= R1[7].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[6] <= R1[6].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[5] <= R1[5].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[4] <= R1[4].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[3] <= R1[3].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[2] <= R1[2].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[1] <= R1[1].DB_MAX_OUTPUT_PORT_TYPE
R1_OUT[0] <= R1[0].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[7] <= R2[7].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[6] <= R2[6].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[5] <= R2[5].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[4] <= R2[4].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[3] <= R2[3].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[2] <= R2[2].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[1] <= R2[1].DB_MAX_OUTPUT_PORT_TYPE
R2_OUT[0] <= R2[0].DB_MAX_OUTPUT_PORT_TYPE