cpu_mm_manager3.tan.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Info" "ITDB_FULL_TPD_RESULT" "Initial DataIn_out\[2\] 13.561 ns Longest " "Info: Longest tpd from source pin Initial to destination pin DataIn_out\[2\] is 13.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns Initial 1 PIN PIN_B17 30 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_B17; Fanout = 30; PIN Node = 'Initial'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { Initial } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.825 ns) + CELL(0.332 ns) 6.298 ns Select4_process~892 2 COMB LC_X34_Y21_N9 2 " "Info: 2: + IC(4.825 ns) + CELL(0.332 ns) = 6.298 ns; Loc. = LC_X34_Y21_N9; Fanout = 2; COMB Node = 'Select4_process~892'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "5.157 ns" { Initial Select4_process~892 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.087 ns) 7.309 ns Select4_process~893 3 COMB LC_X32_Y21_N0 19 " "Info: 3: + IC(0.924 ns) + CELL(0.087 ns) = 7.309 ns; Loc. = LC_X32_Y21_N0; Fanout = 19; COMB Node = 'Select4_process~893'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.011 ns" { Select4_process~892 Select4_process~893 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.748 ns) + CELL(2.504 ns) 13.561 ns DataIn_out\[2\] 4 PIN PIN_D16 0 " "Info: 4: + IC(3.748 ns) + CELL(2.504 ns) = 13.561 ns; Loc. = PIN_D16; Fanout = 0; PIN Node = 'DataIn_out\[2\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "6.252 ns" { Select4_process~893 DataIn_out[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.064 ns 29.97 % " "Info: Total cell delay = 4.064 ns ( 29.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.497 ns 70.03 % " "Info: Total interconnect delay = 9.497 ns ( 70.03 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "13.561 ns" { Initial Select4_process~892 Select4_process~893 DataIn_out[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "ReadMEM reset clk -0.589 ns register " "Info: th for register ReadMEM (data pin = reset, clock pin = clk) is -0.589 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.990 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 219 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 219; CLK Node = 'clk'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.670 ns) + CELL(0.560 ns) 2.990 ns ReadMEM 2 REG LC_X33_Y21_N7 19 " "Info: 2: + IC(1.670 ns) + CELL(0.560 ns) = 2.990 ns; Loc. = LC_X33_Y21_N7; Fanout = 19; REG Node = 'ReadMEM'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.230 ns" { clk ReadMEM } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 44.15 % " "Info: Total cell delay = 1.320 ns ( 44.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.670 ns 55.85 % " "Info: Total interconnect delay = 1.670 ns ( 55.85 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.990 ns" { clk ReadMEM } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.679 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns reset 1 PIN PIN_M26 208 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_M26; Fanout = 208; PIN Node = 'reset'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { reset } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.085 ns) + CELL(0.726 ns) 3.679 ns ReadMEM 2 REG LC_X33_Y21_N7 19 " "Info: 2: + IC(2.085 ns) + CELL(0.726 ns) = 3.679 ns; Loc. = LC_X33_Y21_N7; Fanout = 19; REG Node = 'ReadMEM'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.811 ns" { reset ReadMEM } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.594 ns 43.33 % " "Info: Total cell delay = 1.594 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.085 ns 56.67 % " "Info: Total interconnect delay = 2.085 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.679 ns" { reset ReadMEM } "NODE_NAME" } } }  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.990 ns" { clk ReadMEM } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.679 ns" { reset ReadMEM } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk R1_OUT\[0\] R1\[0\] 7.072 ns register " "Info: Minimum tco from clock clk to destination pin R1_OUT\[0\] through register R1\[0\] is 7.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.955 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 219 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 219; CLK Node = 'clk'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.635 ns) + CELL(0.560 ns) 2.955 ns R1\[0\] 2 REG LC_X40_Y23_N6 2 " "Info: 2: + IC(1.635 ns) + CELL(0.560 ns) = 2.955 ns; Loc. = LC_X40_Y23_N6; Fanout = 2; REG Node = 'R1\[0\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.195 ns" { clk R1[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 44.67 % " "Info: Total cell delay = 1.320 ns ( 44.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.635 ns 55.33 % " "Info: Total interconnect delay = 1.635 ns ( 55.33 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.955 ns" { clk R1[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.941 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns R1\[0\] 1 REG LC_X40_Y23_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y23_N6; Fanout = 2; REG Node = 'R1\[0\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.437 ns) + CELL(2.504 ns) 3.941 ns R1_OUT\[0\] 2 PIN PIN_G19 0 " "Info: 2: + IC(1.437 ns) + CELL(2.504 ns) = 3.941 ns; Loc. = PIN_G19; Fanout = 0; PIN Node = 'R1_OUT\[0\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.941 ns" { R1[0] R1_OUT[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.504 ns 63.54 % " "Info: Total cell delay = 2.504 ns ( 63.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.437 ns 36.46 % " "Info: Total interconnect delay = 1.437 ns ( 36.46 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.941 ns" { R1[0] R1_OUT[0] } "NODE_NAME" } } }  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.955 ns" { clk R1[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.941 ns" { R1[0] R1_OUT[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "InitialData\[4\] DataIn_out\[4\] 10.703 ns Shortest " "Info: Shortest tpd from source pin InitialData\[4\] to destination pin DataIn_out\[4\] is 10.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns InitialData\[4\] 1 PIN PIN_D17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_D17; Fanout = 1; PIN Node = 'InitialData\[4\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.195 ns) + CELL(0.213 ns) 5.549 ns Select4_process~896 2 COMB LC_X35_Y24_N8 2 " "Info: 2: + IC(4.195 ns) + CELL(0.213 ns) = 5.549 ns; Loc. = LC_X35_Y24_N8; Fanout = 2; COMB Node = 'Select4_process~896'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "4.408 ns" { InitialData[4] Select4_process~896 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.341 ns) + CELL(0.087 ns) 5.977 ns Select4_process~897 3 COMB LC_X35_Y24_N2 19 " "Info: 3: + IC(0.341 ns) + CELL(0.087 ns) = 5.977 ns; Loc. = LC_X35_Y24_N2; Fanout = 19; COMB Node = 'Select4_process~897'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "0.428 ns" { Select4_process~896 Select4_process~897 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.222 ns) + CELL(2.504 ns) 10.703 ns DataIn_out\[4\] 4 PIN PIN_E16 0 " "Info: 4: + IC(2.222 ns) + CELL(2.504 ns) = 10.703 ns; Loc. = PIN_E16; Fanout = 0; PIN Node = 'DataIn_out\[4\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "4.726 ns" { Select4_process~897 DataIn_out[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.945 ns 36.86 % " "Info: Total cell delay = 3.945 ns ( 36.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.758 ns 63.14 % " "Info: Total interconnect delay = 6.758 ns ( 63.14 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "10.703 ns" { InitialData[4] Select4_process~896 Select4_process~897 DataIn_out[4] } "NODE_NAME" } } }  } 0}