cpu_mm_manager3.tan.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register IR\[3\] register R2\[4\] 124.69 MHz 8.02 ns Internal " "Info: Clock clk has Internal fmax of 124.69 MHz between source register IR\[3\] and destination register R2\[4\] (period= 8.02 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.840 ns + Longest register register " "Info: + Longest register to register delay is 7.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns IR\[3\] 1 REG LC_X41_Y23_N9 38 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y23_N9; Fanout = 38; REG Node = 'IR\[3\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { IR[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 162 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.687 ns) + CELL(0.459 ns) 1.146 ns OP.idle_t~28 2 COMB LC_X41_Y23_N8 7 " "Info: 2: + IC(0.687 ns) + CELL(0.459 ns) = 1.146 ns; Loc. = LC_X41_Y23_N8; Fanout = 7; COMB Node = 'OP.idle_t~28'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.146 ns" { IR[3] OP.idle_t~28 } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.510 ns) + CELL(0.213 ns) 2.869 ns Select~11264 3 COMB LC_X36_Y21_N1 1 " "Info: 3: + IC(1.510 ns) + CELL(0.213 ns) = 2.869 ns; Loc. = LC_X36_Y21_N1; Fanout = 1; COMB Node = 'Select~11264'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.723 ns" { OP.idle_t~28 Select~11264 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.439 ns) + CELL(0.459 ns) 4.767 ns Select~11266 4 COMB LC_X40_Y22_N4 1 " "Info: 4: + IC(1.439 ns) + CELL(0.459 ns) = 4.767 ns; Loc. = LC_X40_Y22_N4; Fanout = 1; COMB Node = 'Select~11266'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.898 ns" { Select~11264 Select~11266 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.087 ns) 6.093 ns ALU_out\[4\]~1149 5 COMB LC_X40_Y17_N8 3 " "Info: 5: + IC(1.239 ns) + CELL(0.087 ns) = 6.093 ns; Loc. = LC_X40_Y17_N8; Fanout = 3; COMB Node = 'ALU_out\[4\]~1149'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.326 ns" { Select~11266 ALU_out[4]~1149 } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.355 ns) + CELL(0.087 ns) 6.535 ns Select1_process~636 6 COMB LC_X40_Y17_N0 2 " "Info: 6: + IC(0.355 ns) + CELL(0.087 ns) = 6.535 ns; Loc. = LC_X40_Y17_N0; Fanout = 2; COMB Node = 'Select1_process~636'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "0.442 ns" { ALU_out[4]~1149 Select1_process~636 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.090 ns) 7.840 ns R2\[4\] 7 REG LC_X40_Y22_N8 2 " "Info: 7: + IC(1.215 ns) + CELL(0.090 ns) = 7.840 ns; Loc. = LC_X40_Y22_N8; Fanout = 2; REG Node = 'R2\[4\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.305 ns" { Select1_process~636 R2[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.395 ns 17.79 % " "Info: Total cell delay = 1.395 ns ( 17.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.445 ns 82.21 % " "Info: Total interconnect delay = 6.445 ns ( 82.21 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "7.840 ns" { IR[3] OP.idle_t~28 Select~11264 Select~11266 ALU_out[4]~1149 Select1_process~636 R2[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.961 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.961 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 219 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 219; CLK Node = 'clk'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.641 ns) + CELL(0.560 ns) 2.961 ns R2\[4\] 2 REG LC_X40_Y22_N8 2 " "Info: 2: + IC(1.641 ns) + CELL(0.560 ns) = 2.961 ns; Loc. = LC_X40_Y22_N8; Fanout = 2; REG Node = 'R2\[4\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.201 ns" { clk R2[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 44.58 % " "Info: Total cell delay = 1.320 ns ( 44.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.641 ns 55.42 % " "Info: Total interconnect delay = 1.641 ns ( 55.42 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.961 ns" { clk R2[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.955 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 219 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 219; CLK Node = 'clk'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.635 ns) + CELL(0.560 ns) 2.955 ns IR\[3\] 2 REG LC_X41_Y23_N9 38 " "Info: 2: + IC(1.635 ns) + CELL(0.560 ns) = 2.955 ns; Loc. = LC_X41_Y23_N9; Fanout = 38; REG Node = 'IR\[3\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.195 ns" { clk IR[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 162 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 44.67 % " "Info: Total cell delay = 1.320 ns ( 44.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.635 ns 55.33 % " "Info: Total interconnect delay = 1.635 ns ( 55.33 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.955 ns" { clk IR[3] } "NODE_NAME" } } }  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.961 ns" { clk R2[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.955 ns" { clk IR[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 162 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "7.840 ns" { IR[3] OP.idle_t~28 Select~11264 Select~11266 ALU_out[4]~1149 Select1_process~636 R2[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.961 ns" { clk R2[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.955 ns" { clk IR[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "R0\[0\] InitialData\[0\] clk 8.990 ns register " "Info: tsu for register R0\[0\] (data pin = InitialData\[0\], clock pin = clk) is 8.990 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.084 ns + Longest pin register " "Info: + Longest pin to register delay is 12.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns InitialData\[0\] 1 PIN PIN_F21 1 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_F21; Fanout = 1; PIN Node = 'InitialData\[0\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.032 ns) + CELL(0.213 ns) 6.386 ns Select4_process~888 2 COMB LC_X41_Y21_N8 2 " "Info: 2: + IC(5.032 ns) + CELL(0.213 ns) = 6.386 ns; Loc. = LC_X41_Y21_N8; Fanout = 2; COMB Node = 'Select4_process~888'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "5.245 ns" { InitialData[0] Select4_process~888 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.087 ns) 7.715 ns Select4_process~889 3 COMB LC_X32_Y21_N3 19 " "Info: 3: + IC(1.242 ns) + CELL(0.087 ns) = 7.715 ns; Loc. = LC_X32_Y21_N3; Fanout = 19; COMB Node = 'Select4_process~889'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.329 ns" { Select4_process~888 Select4_process~889 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.148 ns) + CELL(0.332 ns) 10.195 ns Select1_process~632 4 COMB LC_X40_Y23_N6 2 " "Info: 4: + IC(2.148 ns) + CELL(0.332 ns) = 10.195 ns; Loc. = LC_X40_Y23_N6; Fanout = 2; COMB Node = 'Select1_process~632'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.480 ns" { Select4_process~889 Select1_process~632 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.654 ns) + CELL(0.235 ns) 12.084 ns R0\[0\] 5 REG LC_X39_Y17_N9 3 " "Info: 5: + IC(1.654 ns) + CELL(0.235 ns) = 12.084 ns; Loc. = LC_X39_Y17_N9; Fanout = 3; REG Node = 'R0\[0\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.889 ns" { Select1_process~632 R0[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.008 ns 16.62 % " "Info: Total cell delay = 2.008 ns ( 16.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.076 ns 83.38 % " "Info: Total interconnect delay = 10.076 ns ( 83.38 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "12.084 ns" { InitialData[0] Select4_process~888 Select4_process~889 Select1_process~632 R0[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.104 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 219 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 219; CLK Node = 'clk'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.784 ns) + CELL(0.560 ns) 3.104 ns R0\[0\] 2 REG LC_X39_Y17_N9 3 " "Info: 2: + IC(1.784 ns) + CELL(0.560 ns) = 3.104 ns; Loc. = LC_X39_Y17_N9; Fanout = 3; REG Node = 'R0\[0\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.344 ns" { clk R0[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 42.53 % " "Info: Total cell delay = 1.320 ns ( 42.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.784 ns 57.47 % " "Info: Total interconnect delay = 1.784 ns ( 57.47 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.104 ns" { clk R0[0] } "NODE_NAME" } } }  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "12.084 ns" { InitialData[0] Select4_process~888 Select4_process~889 Select1_process~632 R0[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "3.104 ns" { clk R0[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk DataIn_out\[2\] R_out\[2\] 11.777 ns register " "Info: tco from clock clk to destination pin DataIn_out\[2\] through register R_out\[2\] is 11.777 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.990 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 219 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 219; CLK Node = 'clk'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.670 ns) + CELL(0.560 ns) 2.990 ns R_out\[2\] 2 REG LC_X34_Y21_N6 13 " "Info: 2: + IC(1.670 ns) + CELL(0.560 ns) = 2.990 ns; Loc. = LC_X34_Y21_N6; Fanout = 13; REG Node = 'R_out\[2\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.230 ns" { clk R_out[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns 44.15 % " "Info: Total cell delay = 1.320 ns ( 44.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.670 ns 55.85 % " "Info: Total interconnect delay = 1.670 ns ( 55.85 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.990 ns" { clk R_out[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.611 ns + Longest register pin " "Info: + Longest register to pin delay is 8.611 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns R_out\[2\] 1 REG LC_X34_Y21_N6 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y21_N6; Fanout = 13; REG Node = 'R_out\[2\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R_out[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.332 ns) 0.769 ns DataOut\[2\]~218 2 COMB LC_X34_Y21_N7 2 " "Info: 2: + IC(0.437 ns) + CELL(0.332 ns) = 0.769 ns; Loc. = LC_X34_Y21_N7; Fanout = 2; COMB Node = 'DataOut\[2\]~218'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "0.769 ns" { R_out[2] DataOut[2]~218 } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.213 ns) 1.348 ns Select4_process~892 3 COMB LC_X34_Y21_N9 2 " "Info: 3: + IC(0.366 ns) + CELL(0.213 ns) = 1.348 ns; Loc. = LC_X34_Y21_N9; Fanout = 2; COMB Node = 'Select4_process~892'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "0.579 ns" { DataOut[2]~218 Select4_process~892 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.087 ns) 2.359 ns Select4_process~893 4 COMB LC_X32_Y21_N0 19 " "Info: 4: + IC(0.924 ns) + CELL(0.087 ns) = 2.359 ns; Loc. = LC_X32_Y21_N0; Fanout = 19; COMB Node = 'Select4_process~893'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "1.011 ns" { Select4_process~892 Select4_process~893 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.748 ns) + CELL(2.504 ns) 8.611 ns DataIn_out\[2\] 5 PIN PIN_D16 0 " "Info: 5: + IC(3.748 ns) + CELL(2.504 ns) = 8.611 ns; Loc. = PIN_D16; Fanout = 0; PIN Node = 'DataIn_out\[2\]'" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "6.252 ns" { Select4_process~893 DataIn_out[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.136 ns 36.42 % " "Info: Total cell delay = 3.136 ns ( 36.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.475 ns 63.58 % " "Info: Total interconnect delay = 5.475 ns ( 63.58 % )" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "8.611 ns" { R_out[2] DataOut[2]~218 Select4_process~892 Select4_process~893 DataIn_out[2] } "NODE_NAME" } } }  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "2.990 ns" { clk R_out[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "8.611 ns" { R_out[2] DataOut[2]~218 Select4_process~892 Select4_process~893 DataIn_out[2] } "NODE_NAME" } } }  } 0}