cpu_mm_manager3.tan.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 09 11:18:40 2005 " "Info: Processing started: Mon May 09 11:18:40 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3 --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3 --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[0\]~216 " "Warning: Node DataOut\[0\]~216 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[1\]~217 " "Warning: Node DataOut\[1\]~217 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[2\]~218 " "Warning: Node DataOut\[2\]~218 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[3\]~219 " "Warning: Node DataOut\[3\]~219 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[4\]~220 " "Warning: Node DataOut\[4\]~220 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[5\]~221 " "Warning: Node DataOut\[5\]~221 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[6\]~222 " "Warning: Node DataOut\[6\]~222 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "DataOut\[7\]~223 " "Warning: Node DataOut\[7\]~223 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[7\]~1152 " "Warning: Node ALU_out\[7\]~1152 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[0\]~1145 " "Warning: Node ALU_out\[0\]~1145 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[2\]~1147 " "Warning: Node ALU_out\[2\]~1147 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[4\]~1149 " "Warning: Node ALU_out\[4\]~1149 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[5\]~1150 " "Warning: Node ALU_out\[5\]~1150 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[6\]~1151 " "Warning: Node ALU_out\[6\]~1151 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[1\]~1146 " "Warning: Node ALU_out\[1\]~1146 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "ALU_out\[3\]~1148 " "Warning: Node ALU_out\[3\]~1148 is a latch" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 -1 0 } }  } 0}  } {  } 0}