cpu_mm_manager3.fit.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock in PIN M26 " "Info: Automatically promoted some destinations of signal reset to use Global clock in PIN M26" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ReadMEM " "Info: Destination ReadMEM may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "WriteMEM " "Info: Destination WriteMEM may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Mem_DataOut\[0\]~28 " "Info: Destination Mem_DataOut\[0\]~28 may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "R_out\[0\] " "Info: Destination R_out\[0\] may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DataOut_to_bus " "Info: Destination DataOut_to_bus may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "R_out\[1\] " "Info: Destination R_out\[1\] may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "R_out\[2\] " "Info: Destination R_out\[2\] may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "R_out\[3\] " "Info: Destination R_out\[3\] may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "R_out\[4\] " "Info: Destination R_out\[4\] may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "R_out\[5\] " "Info: Destination R_out\[5\] may be non-global or may not use global clock" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}