cpu_mm_manager3.fit.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "47 47 " "Info: No exact pin location assignment(s) for 47 pins of 47 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[0\] " "Info: Pin DataIn_out\[0\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[0\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[1\] " "Info: Pin DataIn_out\[1\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[1\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[1] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[2\] " "Info: Pin DataIn_out\[2\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[2\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[3\] " "Info: Pin DataIn_out\[3\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[3\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[4\] " "Info: Pin DataIn_out\[4\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[4\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[5\] " "Info: Pin DataIn_out\[5\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[5\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[5] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[6\] " "Info: Pin DataIn_out\[6\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[6\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[6] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DataIn_out\[7\] " "Info: Pin DataIn_out\[7\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 25 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "DataIn_out\[7\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { DataIn_out[7] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { DataIn_out[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[0\] " "Info: Pin R0_OUT\[0\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[0\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[1\] " "Info: Pin R0_OUT\[1\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[1\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[1] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[2\] " "Info: Pin R0_OUT\[2\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[2\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[3\] " "Info: Pin R0_OUT\[3\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[3\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[4\] " "Info: Pin R0_OUT\[4\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[4\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[5\] " "Info: Pin R0_OUT\[5\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[5\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[5] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[6\] " "Info: Pin R0_OUT\[6\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[6\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[6] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R0_OUT\[7\] " "Info: Pin R0_OUT\[7\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R0_OUT\[7\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R0_OUT[7] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R0_OUT[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[0\] " "Info: Pin R1_OUT\[0\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[0\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[1\] " "Info: Pin R1_OUT\[1\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[1\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[1] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[2\] " "Info: Pin R1_OUT\[2\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[2\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[3\] " "Info: Pin R1_OUT\[3\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[3\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[4\] " "Info: Pin R1_OUT\[4\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[4\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[5\] " "Info: Pin R1_OUT\[5\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[5\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[5] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[6\] " "Info: Pin R1_OUT\[6\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[6\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[6] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R1_OUT\[7\] " "Info: Pin R1_OUT\[7\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R1_OUT\[7\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R1_OUT[7] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R1_OUT[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[0\] " "Info: Pin R2_OUT\[0\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[0\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[1\] " "Info: Pin R2_OUT\[1\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[1\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[1] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[2\] " "Info: Pin R2_OUT\[2\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[2\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[3\] " "Info: Pin R2_OUT\[3\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[3\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[4\] " "Info: Pin R2_OUT\[4\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[4\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[5\] " "Info: Pin R2_OUT\[5\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[5\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[5] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[6\] " "Info: Pin R2_OUT\[6\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[6\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[6] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "R2_OUT\[7\] " "Info: Pin R2_OUT\[7\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 26 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "R2_OUT\[7\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { R2_OUT[7] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { R2_OUT[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[0\] " "Info: Pin InitialData\[0\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[0\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Initial " "Info: Pin Initial not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Initial" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { Initial } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Initial } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[1\] " "Info: Pin InitialData\[1\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[1\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[1] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[2\] " "Info: Pin InitialData\[2\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[2\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[3\] " "Info: Pin InitialData\[3\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[3\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[4\] " "Info: Pin InitialData\[4\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[4\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[4] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[5\] " "Info: Pin InitialData\[5\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[5\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[5] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[6\] " "Info: Pin InitialData\[6\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[6\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[6] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialData\[7\] " "Info: Pin InitialData\[7\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 19 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialData\[7\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialData[7] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialData[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "reset " "Info: Pin reset not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { reset } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { reset } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialAddr\[2\] " "Info: Pin InitialAddr\[2\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 20 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialAddr\[2\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialAddr[2] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialAddr[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialAddr\[3\] " "Info: Pin InitialAddr\[3\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 20 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialAddr\[3\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialAddr[3] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialAddr[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialAddr\[0\] " "Info: Pin InitialAddr\[0\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 20 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialAddr\[0\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialAddr[0] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialAddr[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "InitialAddr\[1\] " "Info: Pin InitialAddr\[1\] not assigned to an exact location on the device" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 20 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "InitialAddr\[1\]" } } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" "" "" { Report "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3_cmp.qrpt" Compiler "cpu_mm_manager3" "UNKNOWN" "V1" "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/db/cpu_mm_manager3.quartus_db" { Floorplan "" "" "" { InitialAddr[1] } "NODE_NAME" } } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { Floorplan "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.fld" "" "" { InitialAddr[1] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN M24 " "Info: Automatically promoted signal clk to use Global clock in PIN M24" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 18 -1 0 } }  } 0}