cpu_mm_manager3.sim.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_out_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_out_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_out_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_to_ALU_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_to_ALU_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_to_ALU_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_to_ALU_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_to_ALU_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_to_ALU_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_in_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_in_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_in_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R_in_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R_in_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R_in_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "OP_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "OP_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "OP_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "OP_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "OP_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "OP_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "OP_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name OP_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "OP_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_in_OUT " "Warning: Ignored node in vector source file. Can't find corresponding node name A_in_OUT in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_in_OUT" "0 ps" "0 ps" "" } }  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     68.96 % " "Info: Simulation coverage is      68.96 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "32838 " "Info: Number of transitions in simulation is 32838" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 75 s " "Info: Quartus II Simulator was successful. 0 errors, 75 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 10 21:37:56 2005 " "Info: Processing ended: Tue May 10 21:37:56 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}