cpu_mm_manager3.sim.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_DataOut_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_DataOut_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_DataOut_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "AddrR_out_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "AddrR_out_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "AddrR_out_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "AddrR_out_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "AddrR_out_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "AddrR_out_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "AddrR_out_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name AddrR_out_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "AddrR_out_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ReadMem_OUT " "Warning: Ignored node in vector source file. Can't find corresponding node name ReadMem_OUT in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ReadMem_OUT" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IP_out_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IP_out_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IP_out_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IP_out_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IP_out_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IP_out_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IP_out_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IP_out_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IP_out_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "A_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name A_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "A_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ALU_out_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name ALU_out_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "ALU_out_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}