cpu_mm_manager3.sim.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 10 21:37:53 2005 " "Info: Processing started: Tue May 10 21:37:53 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --import_settings_files=on --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3 " "Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3" {  } {  } 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "statement~36 " "Warning: Can't display state machine states -- register holding state machine bit statement~36 was synthesized away" {  } {  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "R3_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name R3_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "R3_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "IR_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name IR_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "IR_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[7\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[6\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[5\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[4\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[3\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[2\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[1\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Mem_Data_in_OUT\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name Mem_Data_in_OUT\[0\] in design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "" "" { Waveform "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vwf" "Mem_Data_in_OUT\[0\]" "0 ps" "0 ps" "" } }  } 0}