cpu_mm_manager3.map.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "memaddr cpu_mm_manager3.vhd(1028) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1028): signal or variable memaddr may not be assigned a new value in every possible path through the Process Statement. Signal or variable memaddr holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1028 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "cpudataout cpu_mm_manager3.vhd(1041) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1041): signal or variable cpudataout may not be assigned a new value in every possible path through the Process Statement. Signal or variable cpudataout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1041 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "mem_data_in cpu_mm_manager3.vhd(1054) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1054): signal or variable mem_data_in may not be assigned a new value in every possible path through the Process Statement. Signal or variable mem_data_in holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1054 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "addrr_in cpu_mm_manager3.vhd(1066) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1066): signal or variable addrr_in may not be assigned a new value in every possible path through the Process Statement. Signal or variable addrr_in holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1066 0 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "48 " "Info: Ignored 48 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "48 " "Info: Ignored 48 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_PREPROCESS_STAT" "\|cpu_mm_manager3\|statement 12 0 " "Info: State machine \|cpu_mm_manager3\|statement contains 12 states and 0 state bits" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|cpu_mm_manager3\|statement " "Info: Selected Auto state machine encoding method for state machine \|cpu_mm_manager3\|statement" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|cpu_mm_manager3\|statement " "Info: Encoding result for state machine \|cpu_mm_manager3\|statement" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "12 " "Info: Completed encoding using 12 state bits" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~39 " "Info: Encoded state bit statement~39" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~38 " "Info: Encoded state bit statement~38" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~37 " "Info: Encoded state bit statement~37" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~36 " "Info: Encoded state bit statement~36" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~35 " "Info: Encoded state bit statement~35" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~34 " "Info: Encoded state bit statement~34" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~33 " "Info: Encoded state bit statement~33" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~32 " "Info: Encoded state bit statement~32" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~31 " "Info: Encoded state bit statement~31" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~30 " "Info: Encoded state bit statement~30" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~29 " "Info: Encoded state bit statement~29" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "statement~28 " "Info: Encoded state bit statement~28" {  } {  } 0}  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step0 000000000000 " "Info: State \|cpu_mm_manager3\|statement.step0 uses code string 000000000000" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step_0 000000000011 " "Info: State \|cpu_mm_manager3\|statement.step_0 uses code string 000000000011" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step1 000000000101 " "Info: State \|cpu_mm_manager3\|statement.step1 uses code string 000000000101" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step2 000000001001 " "Info: State \|cpu_mm_manager3\|statement.step2 uses code string 000000001001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step3 000000010001 " "Info: State \|cpu_mm_manager3\|statement.step3 uses code string 000000010001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step01 000000100001 " "Info: State \|cpu_mm_manager3\|statement.step01 uses code string 000000100001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step12 000001000001 " "Info: State \|cpu_mm_manager3\|statement.step12 uses code string 000001000001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step23 000010000001 " "Info: State \|cpu_mm_manager3\|statement.step23 uses code string 000010000001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step00 000100000001 " "Info: State \|cpu_mm_manager3\|statement.step00 uses code string 000100000001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step10 001000000001 " "Info: State \|cpu_mm_manager3\|statement.step10 uses code string 001000000001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step20 010000000001 " "Info: State \|cpu_mm_manager3\|statement.step20 uses code string 010000000001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpu_mm_manager3\|statement.step30 100000000001 " "Info: State \|cpu_mm_manager3\|statement.step30 uses code string 100000000001" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "statement~36 data_in GND " "Warning: Reduced register statement~36 with stuck data_in port to stuck value GND" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer to OR gate or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "DataorALU_to_bus~0 " "Warning: Converting TRI node DataorALU_to_bus~0 that feeds logic to an OR gate" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "IPorAddrOut~0 " "Warning: Converting TRI node IPorAddrOut~0 that feeds logic to an OR gate" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 96 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 914 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } } { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 226 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "658 " "Info: Implemented 658 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "611 " "Info: Implemented 611 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 09 11:17:37 2005 " "Info: Processing ended: Mon May 09 11:17:37 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}