📄 cpu_mm_manager3.vhd
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R_in<="11";
R_to_ALU<="11";
A_in<='0';
when Write_T =>
IPorAddrOut<='1';
ReadMem<='0';
WriteMem<='0';
statement<=Step12;
DataOut_to_bus<='1';------------------pay attention to this to decide if it is right.
IP_in<="00";
IR_in<='0';
R_Enable<='1';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="10";
A_in<='0';
when others => NULL;
END CASE;
when Step2 =>
CASE OP IS
when Add_T|Sub_T |AND_T|OR_T|XOR_T =>
IR_in<='0';
A_in<='0';
R_Enable<='1';
R_in<=IR(4 to 5);
DataorALU_to_bus<='1';
R_to_ALU<="11";
statement<=Step20;
--Done<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
-- when AND_T|OR_T|XOR_T =>
-- IR_in<='0';
-- A_in<='0';
-- R_Enable<='0';
-- R_in<=IR(4 to 5);
-- DataorALU_to_bus<='1';
-- R_to_ALU<="11";
-- statement<=Step20;
-- --Done<='1';
-- IPorAddrOut<='Z';
-- ReadMem<='0';
-- WriteMem<='0';
-- IP_in<="00";
-- DataOut_to_bus<='0';
when Swap_T =>
IR_in<='0';
A_in<='0';
R_Enable<='1';
R_to_ALU<=IR(4 to 5);
R_in<="11";
DataorALU_to_bus<='1';
statement<=Step23;
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Jmp_T | Jz_T =>
IP_in<="00";
ReadMem<='1';
WriteMem<='0';
statement<=Step23;
IPorAddrOut<='Z';
DataOut_to_bus<='0';
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
when Read_T =>
IP_in<="00";
ReadMem<='1';
WriteMem<='0';
statement<=Step23;
IPorAddrOut<='Z';
DataOut_to_bus<='0';
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
when Write_T =>
IP_in<="00";
ReadMem<='0';
WriteMem<='1';
statement<=Step23;
IPorAddrOut<='Z';
DataOut_to_bus<='1';
IR_in<='0';
R_Enable<='1';
DataorALU_to_bus<='Z';
R_in<="11";
R_to_ALU<="10";
A_in<='0';
when others => NULL;
END CASE;
when Step3 =>
CASE OP IS
when Swap_T =>
IR_in<='0';
A_in<='0';
R_to_ALU<="11";
R_Enable<='0';
R_in<=IR(4 to 5);
DataorALU_to_bus<='1';
statement<=Step30;
--Done<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Jmp_T | Jz_T =>
IP_in<="00";
ReadMem<='0'; --------------- similar to : Mem_Data<=Mem_DataOut
WriteMem<='0';
statement<=Step30;
IPorAddrOut<='Z';
DataOut_to_bus<='0';
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
when Read_T =>
DataorALU_to_bus<='0';
ReadMem<='1';
WriteMem<='0';
R_in<="00";
R_Enable<='1';
R_to_ALU<="11";
statement<=Step30;
IPorAddrOut<='Z';
A_in<='0';
when Write_T =>
IP_in<="00";
ReadMem<='0';
WriteMem<='1';
statement<=Step30;
IPorAddrOut<='Z';
DataOut_to_bus<='1';
IR_in<='0';
R_Enable<='1';
DataorALU_to_bus<='Z';
R_in<="11";
R_to_ALU<="10";
A_in<='0';
when others => statement<=Step30;
END CASE;
when Step01 =>
IF OP=Idle_T THEN
statement<=Step0;
Done<='1';
ELSE
CASE OP IS
when Add_T|Sub_T|AND_T|OR_T|XOR_T =>
statement<=Step1;
R_Enable<='1';
R_to_ALU<=IR(6 to 7);
IR_in<='0';
R_in<="11";
A_in<='1';
DataorALU_to_bus<='1';
ReadMem<='0';
IPorAddrOut<='Z';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Shr_T|Shl_T =>
statement<=Step1;
R_Enable<='1';
R_to_ALU<=IR(4 to 5);
IR_in<='0';
R_in<="11";
A_in<='0';
DataorALU_to_bus<='1';
ReadMem<='0';
IPorAddrOut<='Z';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Move_T =>
statement<=Step1;
R_Enable<='1';
R_to_ALU<=IR(6 to 7);
IR_in<='0';
R_in<="11";
A_in<='0';
DataorALU_to_bus<='1';
ReadMem<='0';
IPorAddrOut<='Z';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Swap_T => statement<=Step1;
--when Shr_T | Shl_T => statement<=Step1;
when others => statement<=Step1;
END CASE;
END IF;
when Step12 =>
CASE OP IS
when Add_T|Sub_T | AND_T|OR_T|XOR_T =>
statement<=Step2;
R_to_ALU<=IR(4 to 5);
R_Enable<='1';
R_in<="11";
A_in<='0';
DataorALU_to_bus<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
-- when AND_T|OR_T|XOR_T =>
-- statement<=Step2;
-- R_to_ALU<=IR(4 to 5);
-- R_Enable<='1';
-- R_in<=IR(4 to 5);
-- A_in<='0';
-- DataorALU_to_bus<='1';
-- IPorAddrOut<='Z';
-- ReadMem<='0';
-- WriteMem<='0';
-- IP_in<="00";
-- DataOut_to_bus<='0';
when Swap_T =>
statement<=Step2;
when others => statement<=Step2;
END CASE;
when Step23 =>
CASE OP IS
when Swap_T =>
statement<=Step3;
IR_in<='0';
A_in<='0';
R_Enable<='1';
R_to_ALU<="11";
R_in<=IR(6 to 7);
DataorALU_to_bus<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when others =>
statement<=Step3;
END CASE;
when Step00 => statement<=Step0; IP_in<="10"; Done<='1';
when Step30 =>
CASE OP IS
when Swap_T =>
statement<=Step0;
IR_in<='0';
A_in<='0';
R_to_ALU<="11";
R_Enable<='1';
R_in<=IR(4 to 5);
DataorALU_to_bus<='1';
IP_in<="10";
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
DataOut_to_bus<='0';
Done<='1';
when Jmp_T | Jz_T =>
statement<=Step0;
IP_in<="00";
Done<='1';
when Read_T | Write_T =>
statement<=Step0;
IP_in<="10";
Done<='1';
when others => statement<=Step0; IP_in<="10"; Done<='1';
END CASE;
when Step10 =>
CASE OP IS
when Shr_T | Shl_T =>
R_Enable<='0';
DataorALU_to_bus<='1';
R_to_ALU<="11";
R_in<="11";
IR_in<='0';
A_in<='0';
statement<=Step0;
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="10";
DataOut_to_bus<='0';
Done<='1';
when Move_T =>
R_Enable<='0';
DataorALU_to_bus<='1';
R_to_ALU<="11";
R_in<="11";
IR_in<='0';
A_in<='0';
statement<=Step0;
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="10";
DataOut_to_bus<='0';
Done<='1';
when others => statement<=Step0; Done<='1';
END CASE;
when Step20 =>
CASE OP IS
when Add_T|Sub_T |AND_T|OR_T|XOR_T =>
DataorALU_to_bus<='1';
R_Enable<='1';
R_in<=IR(4 to 5);
R_to_ALU<="11";
IR_in<='0';
A_in<='0';
statement<=Step0;
IP_in<="10";
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
DataOut_to_bus<='0';
Done<='1';
-- when AND_T|OR_T|XOR_T =>
-- DataorALU_to_bus<='1';
-- R_Enable<='0';
-- R_in<="11";
-- R_to_ALU<="11";
-- IR_in<='0';
-- A_in<='0';
-- statement<=Step0;
-- IP_in<="10";
-- IPorAddrOut<='Z';
-- ReadMem<='0';
-- WriteMem<='0';
-- DataOut_to_bus<='0';
-- Done<='1';
when Swap_T => statement<=Step0; IP_in<="10"; Done<='1';
when others => statement<=Step0; IP_in<="10"; Done<='1';
END CASE;
--when others => NULL;
END CASE;
ELSE NULL;
END IF;
END PROCESS;
------------------ the processes i added ----------------------------------------
IP_Process:
PROCESS(reset,clk)
variable counter: integer range 0 to 15;
BEGIN
IF reset='0' THEN
IP_out<="0000";
ELSIF clk'event and clk='1' THEN
CASE IP_in IS
when "11"=> IP_out<=IR(4 to 7);
when "10"=> counter:=CONV_INTEGER(IP_out); counter:=counter+1; IP_out<=CONV_STD_LOGIC_VECTOR(counter,4);
when "00"=> null;
when others => null;
END CASE;
ELSE NULL;
END IF;
END PROCESS;
MM_Process:
PROCESS(reset,clk)
BEGIN
IF reset='0' THEN
MM_RE_0<=X"EC"; -- Write指令,将R2内数据存入MM_RE_C
MM_RE_1<=X"DC"; -- Read 指令,将MM_RE_C内数据读出存入R0寄存器
MM_RE_2<=X"B5"; -- JMP指令,跳到MM_RE_5执行
MM_RE_3<=X"00";
MM_RE_4<=X"00";
MM_RE_5<=X"A1"; -- Swap指令⌨️ 快捷键说明
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