📄 cpu_mm_manager3.vhd
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package my_own is
type Step_statement is ( Step_0,Step0,Step1,Step2,Step3,Step01,Step12,Step23,Step00,Step10,Step20,Step30);
type Operation is (Idle_T,Load_T,Move_T,Add_T,Sub_T,AND_T,OR_T,XOR_T,Shr_T,Shl_T,Swap_T,Read_T,Write_T,Jmp_T,Jz_T,Stop_T);
end my_own;
Library IEEE;
USE Work.my_own.ALL;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.Std_Logic_signed.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY cpu_mm_manager3 IS
PORT (reset,clk,Initial: IN Std_Logic;
InitialData : IN Std_Logic_vector(0 to 7);
InitialAddr : IN Std_Logic_vector(0 to 3);
--DataIn: IN Std_Logic_vector(0 to 7);
--AA,ALU: OUT Std_Logic_vector(0 to 7);
--OP_OUT: OUT Operation;
--Done_out: OUT Std_Logic;
DataIn_out: OUT Std_Logic_vector(0 to 7);
R0_OUT,R1_OUT,R2_OUT: OUT Std_Logic_vector(0 to 7)
);
END cpu_mm_manager3;
ARCHITECTURE CPU_manager_mm_arc3 OF cpu_mm_manager3 IS
SIGNAL A_in,R_Enable,IR_in : Std_Logic;
SIGNAL DataorALU_to_bus : Std_Logic;
SIGNAL R_to_ALU,R_in : Std_Logic_vector (0 to 1);
SIGNAL ALU_fun : Std_Logic_vector(0 to 3);
SIGNAL Bus_Wire,R_out,ALU_out :Std_Logic_vector (0 to 7) ;
SIGNAL A,IR :Std_Logic_vector (0 to 7) ;
SIGNAL R0,R1,R2 :Std_Logic_vector (0 to 7) ;------------------------throw off the R3
SIGNAL Done: Std_Logic;
SIGNAL OP :Operation :=Idle_T;
SIGNAL statement : Step_statement :=Step0;
--SIGNAL counter_sig : Integer range 0 to 9;
----------- the vars i added -----------------
SIGNAL IPorAddrOut,ReadMEM,WriteMEM,DataOut_to_bus : Std_Logic;
SIGNAL IP_in : Std_Logic_vector (0 to 1);
SIGNAL IP_out : Std_Logic_vector (0 to 3);
SIGNAL MemAddr: Std_Logic_vector (0 to 3);
SIGNAL AddrR_in : Std_Logic_vector (0 to 3);
SIGNAL AddrR_out: Std_Logic_vector (0 to 3);
SIGNAL DataOut: Std_Logic_vector (0 to 7);
SIGNAL DataIn : Std_Logic_vector (0 to 7);
SIGNAL CPUDataOut : Std_Logic_vector (0 to 7);
SIGNAL Mem_DataOut: Std_Logic_vector (0 to 7);
SIGNAL Mem_Data_in: Std_Logic_vector (0 to 7);
SIGNAL Mem_Data : Std_Logic_vector (0 to 7);
SIGNAL Mem_DataIn : Std_Logic_vector (0 to 7);
------------------------------------------------
----------- The MM Registers 16 ----------------
SIGNAL MM_RE_0,MM_RE_1,MM_RE_2,MM_RE_3 : Std_Logic_vector (0 to 7);
SIGNAL MM_RE_4,MM_RE_5,MM_RE_6,MM_RE_7 : Std_Logic_vector (0 to 7);
SIGNAL MM_RE_8,MM_RE_9,MM_RE_A,MM_RE_B : Std_Logic_vector (0 to 7);
SIGNAL MM_RE_C,MM_RE_D,MM_RE_E,MM_RE_F : Std_Logic_vector (0 to 7);
------------------------------------------------
BEGIN
foroutput: BLOCK
BEGIN
R0_OUT<=R0;
R1_OUT<=R1;
R2_OUT<=R2;
--R3_OUT<=R3;
--Done_out<=Done;
--ALU<=ALU_OUT;
--OP_OUT<=OP;
DataIn_out<=DataIn;
END BLOCK;
Registers_process:
PROCESS(reset,clk)
BEGIN
IF reset='0' THEN
R0<="01100101";
R1<="00001011";
R2<="00000111";
--R3<="00000000";
ELSIF clk'event and clk='1' THEN
IF R_Enable='1' THEN
CASE R_in IS
when "00"=> R0<=Bus_Wire; IF OP=Load_T THEN R0(0 to 3)<="0000"; ELSE NULL; END IF;
when "01"=> R1<=Bus_Wire;
when "10"=> R2<=Bus_Wire;
--when "11"=> R3<=Bus_Wire;
when others=> null;
END CASE;
ELSE NULL;
END IF;
CASE R_to_ALU IS
when "00"=> R_out<=R0;
when "01"=> R_out<=R1;
when "10"=> R_out<=R2;
--when "11"=> R_out<=R3;
when others=> null;
END CASE;
ELSE NULL;
END IF;
END PROCESS;
Select1_process:
PROCESS(DataorALU_to_bus,DataIn,ALU_out)
BEGIN
IF DataorALU_to_bus='0' THEN
Bus_Wire<=DataIn;
ELSIF DataorALU_to_bus='1' THEN
Bus_Wire<=ALU_out;
ELSE NULL;
END IF;
END PROCESS;
A_process:
PROCESS(reset,clk)
BEGIN
IF reset='0' THEN
A<="00000000";
ELSIF clk'event and clk='1' THEN
IF A_in='1' THEN
A<=R_out;
--AA<=R_out;
ELSE NULL;
END IF;
ELSE NULL;
END IF;
END PROCESS;
IR_process:
PROCESS(reset,clk)
BEGIN
IF reset='0' THEN
IR<="00000000";
ELSIF clk'event and clk='1' THEN
IF IR_in='1' THEN
IR<=DataIn;
ELSE NULL;
END IF;
ELSE NULL;
END IF;
END PROCESS;
ALU_process:
PROCESS(IR,R_out,A)
variable OP_v : Operation;
BEGIN
ALU_fun<=IR(0 to 3);
CASE IR(0 to 3) IS
when "0000"=> OP_v:=Idle_T;
when "0001"=> OP_v:=Load_T;
when "0010"=> OP_v:=Move_T;
when "0011"=> OP_v:=Add_T;
when "0100"=> OP_v:=Sub_T;
when "0101"=> OP_v:=AND_T;
when "0110"=> OP_v:=OR_T;
when "0111"=> OP_v:=XOR_T;
when "1000"=> OP_v:=Shr_T;
when "1001"=> OP_v:=Shl_T;
when "1010"=> OP_v:=Swap_T;
when "1011"=> OP_v:=Jmp_T;
when "1100"=> OP_v:=Jz_T;
when "1101"=> OP_v:=Read_T;
when "1110"=> OP_v:=Write_T;
when "1111"=> OP_v:=Stop_T;
when others=> null;
END CASE;
OP<=OP_v;
CASE OP_v IS
when Idle_T => null;
when Move_T => ALU_out<=R_out;
when Add_T => ALU_out<=R_out+A;
when Sub_T => ALU_out<=R_out-A;
when AND_T => ALU_out<=R_out and A;
when OR_T => ALU_out<=R_out or A;
when XOR_T => ALU_out<=R_out xor A;
when Shr_T => ALU_out(1 to 7)<=R_out(0 to 6); ALU_out(0)<='0';
when Shl_T => ALU_out(0 to 6)<=R_out(1 to 7); ALU_out(7)<='0';
when Swap_T =>IF statement=Step2 or statement=Step12 or statement=Step23 or statement=Step3 THEN
ALU_out<=R_out;
ELSIF statement=Step30 THEN
ALU_out<=A;
ELSE NULL;
END IF;
when others=> null;
END CASE;
END PROCESS;
control_process_2:
PROCESS(reset,clk)
--variable counter1 : Integer range 0 to 9;
BEGIN
IF reset='0' THEN
statement<=Step0;
Done<='1';
IR_in<='0';
A_in<='0';
R_Enable<='0';
R_in<="11";
DataorALU_to_bus<='1';-----X
R_to_ALU<="11";
ELSIF clk'event and clk='1' THEN
CASE statement IS
when Step0 =>
IPorAddrOut<='0';
ReadMem<='1';
statement<=Step_0;
Done<='0';
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Step_0 =>
case OP is
when Add_T | Sub_T |AND_T |OR_T |XOR_T =>
IR_in<='1';
R_Enable<='1';
DataorALU_to_bus<='1';----X
R_in<="11";
R_to_ALU<=IR(6 to 7);
A_in<='0';
IPorAddrOut<='0';
ReadMem<='1';
statement<=Step01;
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Shr_T | Shl_T =>
IR_in<='1';
R_Enable<='1';
DataorALU_to_bus<='1';----X
R_in<="11";
R_to_ALU<=IR(4 to 5);
A_in<='0';
IPorAddrOut<='0';
ReadMem<='1';
statement<=Step01;
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Move_T =>
IR_in<='1';
R_Enable<='1';
DataorALU_to_bus<='1';----X
R_in<="11";
R_to_ALU<=IR(6 to 7);
A_in<='0';
IPorAddrOut<='0';
ReadMem<='1';
statement<=Step01;
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when others =>
IR_in<='1';
R_Enable<='0';
DataorALU_to_bus<='1';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
IPorAddrOut<='0';
ReadMem<='1';
statement<=Step01;
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
end case;
when Step1 =>
CASE OP IS
when Load_T =>
IR_in<='0';
R_to_ALU<="11";
A_in<='0';
R_Enable<='1';
R_in<="00";
DataorALU_to_bus<='0';
statement<=Step10;
--Done<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Move_T =>
IR_in<='0';
A_in<='0';
R_Enable<='1';
R_to_ALU<="11";
R_in<=IR(4 to 5);
DataorALU_to_bus<='1';
statement<=Step10;
--Done<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Add_T|Sub_T|AND_T|OR_T|XOR_T =>
IR_in<='0';
R_in<="11";
DataorALU_to_bus<='1';------X
R_to_ALU<=IR(6 to 7);
R_Enable<='0';
A_in<='0';
statement<=Step12;
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Shr_T|Shl_T =>
IR_in<='0';
A_in<='0';
R_Enable<='1';
DataorALU_to_bus<='1';
R_to_ALU<="11";
R_in<=IR(4 to 5);
statement<=Step10;
--Done<='1';
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Swap_T =>
IR_in<='0';
R_in<="11";
DataorALU_to_bus<='1';------X
R_to_ALU<=IR(6 to 7);
R_Enable<='1';
A_in<='1';
statement<=Step12;
IPorAddrOut<='Z';
ReadMem<='0';
WriteMem<='0';
IP_in<="00";
DataOut_to_bus<='0';
when Jmp_T =>
IP_in<="11";
ReadMem<='0';
WriteMem<='0';
statement<=Step12;
IPorAddrOut<='Z';
DataOut_to_bus<='0';
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
when Jz_T =>
IF R0=X"00" THEN
IP_in<="11";
ReadMem<='0';
WriteMem<='0';
statement<=Step12;
IPorAddrOut<='Z';
DataOut_to_bus<='0';
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
R_in<="11";
R_to_ALU<="11";
A_in<='0';
ELSE NULL;
END IF;
when Read_T =>
IPorAddrOut<='1';
ReadMem<='1';
WriteMem<='0';
statement<=Step12;
DataOut_to_bus<='1';------------------pay attention to this to decide if it is right.
IP_in<="00";
IR_in<='0';
R_Enable<='0';
DataorALU_to_bus<='Z';----X
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