cpu_mm_manager3.map.eqn

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

MM_RE_4[6]_lut_out = A1L835;
MM_RE_4[6] = DFFEA(MM_RE_4[6]_lut_out, clk, reset, , A1L981, , );


--A1L883 is Mux~1249
--operation mode is normal

A1L883 = AddrR_out[2] & (AddrR_out[3] # MM_RE_6[6]) # !AddrR_out[2] & !AddrR_out[3] & MM_RE_4[6];


--MM_RE_7[6] is MM_RE_7[6]
--operation mode is normal

MM_RE_7[6]_lut_out = A1L835;
MM_RE_7[6] = DFFEA(MM_RE_7[6]_lut_out, clk, reset, , A1L912, , );


--A1L983 is Mux~1250
--operation mode is normal

A1L983 = A1L883 & (MM_RE_7[6] # !AddrR_out[3]) # !A1L883 & MM_RE_5[6] & AddrR_out[3];


--MM_RE_2[6] is MM_RE_2[6]
--operation mode is normal

MM_RE_2[6]_lut_out = A1L835;
MM_RE_2[6] = DFFEA(MM_RE_2[6]_lut_out, clk, reset, , A1L961, , );


--MM_RE_1[6] is MM_RE_1[6]
--operation mode is normal

MM_RE_1[6]_lut_out = A1L835;
MM_RE_1[6] = DFFEA(MM_RE_1[6]_lut_out, clk, reset, , A1L951, , );


--MM_RE_0[6] is MM_RE_0[6]
--operation mode is normal

MM_RE_0[6]_lut_out = A1L835;
MM_RE_0[6] = DFFEA(MM_RE_0[6]_lut_out, clk, reset, , A1L941, , );


--A1L683 is Mux~1247
--operation mode is normal

A1L683 = AddrR_out[3] & (AddrR_out[2] # MM_RE_1[6]) # !AddrR_out[3] & !AddrR_out[2] & MM_RE_0[6];


--MM_RE_3[6] is MM_RE_3[6]
--operation mode is normal

MM_RE_3[6]_lut_out = A1L835;
MM_RE_3[6] = DFFEA(MM_RE_3[6]_lut_out, clk, reset, , A1L971, , );


--A1L783 is Mux~1248
--operation mode is normal

A1L783 = A1L683 & (MM_RE_3[6] # !AddrR_out[2]) # !A1L683 & MM_RE_2[6] & AddrR_out[2];


--A1L583 is Mux~1245
--operation mode is normal

A1L583 = AddrR_out[1] & (AddrR_out[0] # A1L983) # !AddrR_out[1] & !AddrR_out[0] & A1L783;


--MM_RE_D[6] is MM_RE_D[6]
--operation mode is normal

MM_RE_D[6]_lut_out = A1L835;
MM_RE_D[6] = DFFEA(MM_RE_D[6]_lut_out, clk, reset, , A1L972, , );


--MM_RE_E[6] is MM_RE_E[6]
--operation mode is normal

MM_RE_E[6]_lut_out = A1L835;
MM_RE_E[6] = DFFEA(MM_RE_E[6]_lut_out, clk, reset, , A1L982, , );


--MM_RE_C[6] is MM_RE_C[6]
--operation mode is normal

MM_RE_C[6]_lut_out = A1L835;
MM_RE_C[6] = DFFEA(MM_RE_C[6]_lut_out, clk, reset, , A1L962, , );


--A1L293 is Mux~1253
--operation mode is normal

A1L293 = AddrR_out[2] & (AddrR_out[3] # MM_RE_E[6]) # !AddrR_out[2] & !AddrR_out[3] & MM_RE_C[6];


--MM_RE_F[6] is MM_RE_F[6]
--operation mode is normal

MM_RE_F[6]_lut_out = A1L835;
MM_RE_F[6] = DFFEA(MM_RE_F[6]_lut_out, clk, reset, , A1L992, , );


--A1L393 is Mux~1254
--operation mode is normal

A1L393 = A1L293 & (MM_RE_F[6] # !AddrR_out[3]) # !A1L293 & MM_RE_D[6] & AddrR_out[3];


--R_out[6] is R_out[6]
--operation mode is normal

R_out[6]_lut_out = A1L923 & (R_to_ALU[0] # R_out[6]) # !A1L923 & !R2[6] & !R_to_ALU[0];
R_out[6] = DFFEA(R_out[6]_lut_out, clk, VCC, , reset, , );


--A1L49 is DataOut[6]~222
--operation mode is normal

A1L49 = LCELL(R_out[6] & (A1L49 # DataOut_to_bus) # !R_out[6] & A1L49 & !DataOut_to_bus);


--MM_RE_5[7] is MM_RE_5[7]
--operation mode is normal

MM_RE_5[7]_lut_out = !A1L045;
MM_RE_5[7] = DFFEA(MM_RE_5[7]_lut_out, clk, reset, , A1L991, , );


--MM_RE_6[7] is MM_RE_6[7]
--operation mode is normal

MM_RE_6[7]_lut_out = !A1L045;
MM_RE_6[7] = DFFEA(MM_RE_6[7]_lut_out, clk, reset, , A1L902, , );


--MM_RE_4[7] is MM_RE_4[7]
--operation mode is normal

MM_RE_4[7]_lut_out = A1L045;
MM_RE_4[7] = DFFEA(MM_RE_4[7]_lut_out, clk, reset, , A1L981, , );


--A1L793 is Mux~1259
--operation mode is normal

A1L793 = AddrR_out[2] & (AddrR_out[3] # !MM_RE_6[7]) # !AddrR_out[2] & !AddrR_out[3] & MM_RE_4[7];


--MM_RE_7[7] is MM_RE_7[7]
--operation mode is normal

MM_RE_7[7]_lut_out = !A1L045;
MM_RE_7[7] = DFFEA(MM_RE_7[7]_lut_out, clk, reset, , A1L912, , );


--A1L893 is Mux~1260
--operation mode is normal

A1L893 = A1L793 & (!MM_RE_7[7] # !AddrR_out[3]) # !A1L793 & !MM_RE_5[7] & AddrR_out[3];


--MM_RE_A[7] is MM_RE_A[7]
--operation mode is normal

MM_RE_A[7]_lut_out = A1L045;
MM_RE_A[7] = DFFEA(MM_RE_A[7]_lut_out, clk, reset, , A1L942, , );


--MM_RE_9[7] is MM_RE_9[7]
--operation mode is normal

MM_RE_9[7]_lut_out = !A1L045;
MM_RE_9[7] = DFFEA(MM_RE_9[7]_lut_out, clk, reset, , A1L932, , );


--MM_RE_8[7] is MM_RE_8[7]
--operation mode is normal

MM_RE_8[7]_lut_out = A1L045;
MM_RE_8[7] = DFFEA(MM_RE_8[7]_lut_out, clk, reset, , A1L922, , );


--A1L993 is Mux~1261
--operation mode is normal

A1L993 = AddrR_out[3] & (AddrR_out[2] # !MM_RE_9[7]) # !AddrR_out[3] & !AddrR_out[2] & MM_RE_8[7];


--MM_RE_B[7] is MM_RE_B[7]
--operation mode is normal

MM_RE_B[7]_lut_out = A1L045;
MM_RE_B[7] = DFFEA(MM_RE_B[7]_lut_out, clk, reset, , A1L952, , );


--A1L004 is Mux~1262
--operation mode is normal

A1L004 = A1L993 & (MM_RE_B[7] # !AddrR_out[2]) # !A1L993 & MM_RE_A[7] & AddrR_out[2];


--MM_RE_2[7] is MM_RE_2[7]
--operation mode is normal

MM_RE_2[7]_lut_out = !A1L045;
MM_RE_2[7] = DFFEA(MM_RE_2[7]_lut_out, clk, reset, , A1L961, , );


--MM_RE_1[7] is MM_RE_1[7]
--operation mode is normal

MM_RE_1[7]_lut_out = A1L045;
MM_RE_1[7] = DFFEA(MM_RE_1[7]_lut_out, clk, reset, , A1L951, , );


--MM_RE_0[7] is MM_RE_0[7]
--operation mode is normal

MM_RE_0[7]_lut_out = A1L045;
MM_RE_0[7] = DFFEA(MM_RE_0[7]_lut_out, clk, reset, , A1L941, , );


--A1L593 is Mux~1257
--operation mode is normal

A1L593 = AddrR_out[3] & (AddrR_out[2] # MM_RE_1[7]) # !AddrR_out[3] & !AddrR_out[2] & MM_RE_0[7];


--MM_RE_3[7] is MM_RE_3[7]
--operation mode is normal

MM_RE_3[7]_lut_out = A1L045;
MM_RE_3[7] = DFFEA(MM_RE_3[7]_lut_out, clk, reset, , A1L971, , );


--A1L693 is Mux~1258
--operation mode is normal

A1L693 = A1L593 & (MM_RE_3[7] # !AddrR_out[2]) # !A1L593 & !MM_RE_2[7] & AddrR_out[2];


--A1L493 is Mux~1255
--operation mode is normal

A1L493 = AddrR_out[0] & (AddrR_out[1] # A1L004) # !AddrR_out[0] & !AddrR_out[1] & A1L693;


--MM_RE_D[7] is MM_RE_D[7]
--operation mode is normal

MM_RE_D[7]_lut_out = A1L045;
MM_RE_D[7] = DFFEA(MM_RE_D[7]_lut_out, clk, reset, , A1L972, , );


--MM_RE_E[7] is MM_RE_E[7]
--operation mode is normal

MM_RE_E[7]_lut_out = A1L045;
MM_RE_E[7] = DFFEA(MM_RE_E[7]_lut_out, clk, reset, , A1L982, , );


--MM_RE_C[7] is MM_RE_C[7]
--operation mode is normal

MM_RE_C[7]_lut_out = A1L045;
MM_RE_C[7] = DFFEA(MM_RE_C[7]_lut_out, clk, reset, , A1L962, , );


--A1L104 is Mux~1263
--operation mode is normal

A1L104 = AddrR_out[2] & (AddrR_out[3] # MM_RE_E[7]) # !AddrR_out[2] & !AddrR_out[3] & MM_RE_C[7];


--MM_RE_F[7] is MM_RE_F[7]
--operation mode is normal

MM_RE_F[7]_lut_out = A1L045;
MM_RE_F[7] = DFFEA(MM_RE_F[7]_lut_out, clk, reset, , A1L992, , );


--A1L204 is Mux~1264
--operation mode is normal

A1L204 = A1L104 & (MM_RE_F[7] # !AddrR_out[3]) # !A1L104 & MM_RE_D[7] & AddrR_out[3];


--R_out[7] is R_out[7]
--operation mode is normal

R_out[7]_lut_out = A1L033 & (R_to_ALU[1] # R_out[7]) # !A1L033 & !R1[7] & !R_to_ALU[1];
R_out[7] = DFFEA(R_out[7]_lut_out, clk, VCC, , reset, , );


--A1L69 is DataOut[7]~223
--operation mode is normal

A1L69 = LCELL(R_out[7] & (A1L69 # DataOut_to_bus) # !R_out[7] & A1L69 & !DataOut_to_bus);


--DataorALU_to_bus is DataorALU_to_bus
--operation mode is normal

DataorALU_to_bus_lut_out = !A1L585 & A1L785 & (!A1L214 # !A1L417Q);
DataorALU_to_bus = DFFEA(DataorALU_to_bus_lut_out, clk, reset, , A1L695, , );


--A1L17Q is control_process_2~3
--operation mode is normal

A1L17Q_lut_out = !A1L795 & !A1L895 & !A1L995 & A1L785;
A1L17Q = DFFEA(A1L17Q_lut_out, clk, reset, , A1L695, , );


--A1L715 is Select1_process~632
--operation mode is normal

A1L715 = DataorALU_to_bus & (A1L17Q & A1L94 # !A1L17Q & A1L625) # !DataorALU_to_bus & A1L94;


--A1L304 is OP.idle_t~20
--operation mode is normal

A1L304 = IR[3] & !IR[2] & !IR[1] & !IR[0];


--R_in[1] is R_in[1]
--operation mode is normal

R_in[1]_lut_out = !A1L106 & !A1L506 & !A1L316 & A1L265;
R_in[1] = DFFEA(R_in[1]_lut_out, clk, reset, , , , );


--R_Enable is R_Enable
--operation mode is normal

R_Enable_lut_out = A1L916 # R_Enable & (A1L026 # !A1L126);
R_Enable = DFFEA(R_Enable_lut_out, clk, reset, , , , );


--R_in[0] is R_in[0]
--operation mode is normal

R_in[0]_lut_out = !A1L326 & !A1L626 & !A1L336 & A1L265;
R_in[0] = DFFEA(R_in[0]_lut_out, clk, reset, , , , );


--A1L224 is R0[0]~4
--operation mode is normal

A1L224 = R_in[1] & R_Enable & R_in[0];


--A1L815 is Select1_process~633
--operation mode is normal

A1L815 = DataorALU_to_bus & (A1L17Q & A1L15 # !A1L17Q & A1L825) # !DataorALU_to_bus & A1L15;


--A1L915 is Select1_process~634
--operation mode is normal

A1L915 = DataorALU_to_bus & (A1L17Q & A1L35 # !A1L17Q & A1L035) # !DataorALU_to_bus & A1L35;


--A1L025 is Select1_process~635
--operation mode is normal

A1L025 = DataorALU_to_bus & (A1L17Q & A1L55 # !A1L17Q & A1L235) # !DataorALU_to_bus & A1L55;


--A1L125 is Select1_process~636
--operation mode is normal

A1L125 = DataorALU_to_bus & (A1L17Q & A1L75 # !A1L17Q & A1L435) # !DataorALU_to_bus & A1L75;


--A1L225 is Select1_process~637
--operation mode is normal

A1L225 = DataorALU_to_bus & (A1L17Q & A1L95 # !A1L17Q & A1L635) # !DataorALU_to_bus & A1L95;


--A1L325 is Select1_process~638
--operation mode is normal

A1L325 = DataorALU_to_bus & (A1L17Q & A1L16 # !A1L17Q & A1L835) # !DataorALU_to_bus & A1L16;


--A1L425 is Select1_process~639
--operation mode is normal

A1L425 = DataorALU_to_bus & (A1L17Q & A1L36 # !A1L17Q & A1L045) # !DataorALU_to_bus & A1L36;


--A1L144 is R1[0]~0
--operation mode is normal

A1L144 = R_Enable & R_in[0] & !R_in[1];


--A1L064 is R2[0]~28
--operation mode is normal

A1L064 = R_in[1] & R_Enable & !R_in[0];


--A1L713 is Mux~1111
--operation mode is normal

A1L713 = !AddrR_out[3] & AddrR_out[2] & !AddrR_out[1] & AddrR_out[0];


--A1L942 is MM_RE_A[0]~0
--operation mode is normal

A1L942 = A1L713 & (Initial # WriteMEM);


--IP_out[2] is IP_out[2]
--operation mode is normal

IP_out[2]_lut_out = IP_in[1] & IR[6] # !IP_in[1] & (IP_out[2] $ IP_out[3]);
IP_out[2] = DFFEA(IP_out[2]_lut_out, clk, reset, , IP_in[0], , );


--IR[6] is IR[6]
--operation mode is normal

IR[6]_lut_out = A1L835;
IR[6] = DFFEA(IR[6]_lut_out, clk, reset, , IR_in, , );


--IPorAddrOut is IPorAddrOut
--operation mode is normal

IPorAddrOut_lut_out = A1L145;
IPorAddrOut = DFFEA(IPorAddrOut_lut_out, clk, VCC, , A1L07, , );


--A1L96Q is control_process_2~0
--operation mode is normal

A1L96Q_lut_out = A1L217Q & (A1L874 # !A1L115) # !A1L295;
A1L96Q = DFFEA(A1L96Q_lut_out, clk, VCC, , A1L07, , );


--A1L421 is IPorAddrOut~9
--operation mode is normal

A1L421 = IPorAddrOut # !A1L96Q;


--A1L31 is AddrR_out[0]~38
--operation mode is normal

A1L31 = reset & (ReadMEM # Initial # WriteMEM);


--A1L613 is Mux~1110
--operation mode is normal

A1L613 = AddrR_out[3] & !AddrR_out[2] & !AddrR_out[1] & AddrR_out[0];


--A1L932 is MM_RE_9[0]~0
--operation mode is normal

A1L932 = A1L613 & (Initial # WriteMEM);


--IP_out[3] is IP_out[3]
--operation mode is normal

IP_out[3]_lut_out = IR[7] & (IP_in[1] # !IP_out[3]) # !IR[7] & !IP_in[1] & !IP_out[3];
IP_out[3] = DFFEA(IP_out[3]_lut_out, clk, reset, , IP_in[0], , );


--IR[7] is IR[7]
--operation mode is normal

IR[7]_lut_out = A1L045;
IR[7] = DFFEA(IR[7]_lut_out, clk, reset, , IR_in, , );


--A1L513 is Mux~1109
--operation mode is normal

A1L513 = !AddrR_out[3] & !AddrR_out[2] & !AddrR_out[1] & AddrR_out[0];


--A1L922 is MM_RE_8[0]~0
--operation mode is normal

A1L922 = A1L513 & (Initial # WriteMEM);


--A1L813 is Mux~1112
--operation mode is normal

A1L813 = AddrR_out[3] & AddrR_out[2] & !AddrR_out[1] & AddrR_out[0];


--A1L952 is MM_RE_B[0]~0
--operation mode is normal

A1L952 = A1L813 & (Initial # WriteMEM);


--IP_out[0] is IP_out[0]
--operation mode is normal

IP_out[0]_lut_out = IP_in[1] & IR[4] # !IP_in[1] & (IP_out[0] $ A1L81);
IP_out[0] = DFFEA(IP_out[0]_lut_out, clk, reset, , IP_in[0], , );


--IR[4] is IR[4]
--operation mode is normal

IR[4]_lut_out = A1L435;
IR[4] = DFFEA(IR[4]_lut_out, clk, reset, , IR_in, , );


--A1L213 is Mux~1106
--operation mode is normal

A1L213 = AddrR_out[3] & !AddrR_out[2] & AddrR_out[1] & !AddrR_out[0];


--A1L991 is MM_RE_5[0]~0
--operation mode is normal

A1L991 = A1L213 & (Initial # WriteMEM);


--A1L313 is Mux~1107
--operation mode is normal

A1L313 = !AddrR_out[3] & AddrR_out[2] & AddrR_out[1] & !AddrR_out[0];


--A1L902 is MM_RE_6[0]~0
--operation mode is normal

A1L902 = A1L313 & (Initial # WriteMEM);


--A1L113 is Mux~1105
--operation mode is normal

A1L113 = !AddrR_out[3] & !AddrR_out[2] & AddrR_out[1] & !AddrR_out[0];


--A1L981 is MM_RE_4[0]~0
--operation mode is normal

A1L981 = A1L113 & (Initial # WriteMEM);


--A1L413 is Mux~1108
--operation mode is normal

A1L413 = AddrR_out[3] & AddrR_out[2] & AddrR_out[1] & !AddrR_out[0];


--A1L912 is MM_RE_7[0]~0
--operation mode is normal

A1L912 = A1L413 & (Initial # WriteMEM);


--IP_out[1] is IP_out[1]
--operation mode is normal

IP_out[1]_lut_out = IP_in[1] & IR[5] # !IP_in[1] & (IP_out[1] $ A1L71);
IP_out[1] = DFFEA(IP_out[1]_lut_out, clk, reset, , IP_in[0], , );


--IR[5] is IR[5]
--operation mode is normal

IR[5]_lut_out = A1L635;